The PMCR_EL0 characteristics are:
Provides details of the Performance Monitors implementation, including the number of counters implemented, and configures and controls the counters.
External register PMCR_EL0 bits [63:32] are architecturally mapped to AArch64 System register PMCR_EL0[63:32] when FEAT_PMUv3_EXT64 is implemented.
External register PMCR_EL0 bits [31:0] are architecturally mapped to AArch64 System register PMCR_EL0[31:0].
External register PMCR_EL0 bits [10:0] are architecturally mapped to AArch32 System register PMCR[10:0].
This register is present only when FEAT_PMUv3_EXT is implemented. Otherwise, direct accesses to PMCR_EL0 are RES0.
PMCR_EL0 is in the Core power domain.
This register is only partially mapped to the internal PMCR System register. An external agent must use other means to discover the information held in PMCR[31:11], such as accessing PMCFGR and the ID registers.
PMCR_EL0 is a:
This register is part of the PMU block.
| 63 | 62 | 61 | 60 | 59 | 58 | 57 | 56 | 55 | 54 | 53 | 52 | 51 | 50 | 49 | 48 | 47 | 46 | 45 | 44 | 43 | 42 | 41 | 40 | 39 | 38 | 37 | 36 | 35 | 34 | 33 | 32 |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RES0 | FZS | ||||||||||||||||||||||||||||||
| RAZ/WI | RES0 | FZO | RES0 | LP | LC | DP | X | D | C | P | E | ||||||||||||||||||||
Reserved, RES0.
Freeze-on-SPE event. Stop counters when PMBLIMITR_EL1.{PMFZ,E} == {1,1} and PMBSR_EL1.S == 1.
| FZS | Meaning |
|---|---|
| 0b0 |
Do not freeze on a Statistical Profiling Buffer Management event. |
| 0b1 |
Affected counters do not count following a Statistical Profiling Buffer Management event. |
The counters affected by this field are:
The same counters are affected even when EL2 is disabled in the current Security state.
Other event counters are not affected by this field.
When PMCR_EL0.DP is 0, PMCCNTR_EL0 is not affected by this field.
The reset behavior of this field is:
Freeze-on-SPE event. Stop counters when PMBLIMITR_EL1.{PMFZ,E} == {1,1} and PMBSR_EL1.S == 1.
| FZS | Meaning |
|---|---|
| 0b0 |
Do not freeze on Statistical Profiling Buffer Management event. |
| 0b1 |
Event counter PMEVCNTR<n>_EL0 does not count following a Statistical Profiling Buffer Management event if n is in the range of affected event counters. |
The counters affected by this field are:
The same counters are affected even when EL2 is disabled in the current Security state.
Other event counters and PMCCNTR_EL0 are not affected by this field.
The reset behavior of this field is:
Reserved, RES0.
Reserved, RAZ/WI.
Hardware must implement this field as RAZ/WI. Software must not rely on the register reading as zero, and must use a read-modify-write sequence to write to the register.
Reserved, RES0.
Freeze-on-overflow. Stop event counters on overflow.
In the description of this field:
| FZO | Meaning |
|---|---|
| 0b0 |
Do not freeze on overflow. |
| 0b1 | Affected counters do not count when any of the following applies:
|
The counters affected by this field are:
Other event counters are not affected by this field.
When PMCR_EL0.DP is 0, PMCCNTR_EL0 is not affected by this field.
The reset behavior of this field is:
Reserved, RES0.
Reserved, RES0.
Long event counter enable. Determines when unsigned overflow is recorded by an event counter overflow bit.
In the description of this field:
If EL2 is implemented and is using AArch32, then PMN is HDCR.HPMN.
If EL2 is implemented and is using AArch64, then PMN is MDCR_EL2.HPMN.
If EL2 is not implemented, then PMN is PMCR_EL0.N.
| LP | Meaning |
|---|---|
| 0b0 |
Event counter overflow on increment that causes unsigned overflow of PMEVCNTR<n>_EL0[31:0]. |
| 0b1 |
Event counter overflow on increment that causes unsigned overflow of PMEVCNTR<n>_EL0[63:0]. |
When FEAT_EBEP is implemented and the PMU exception is enabled, the Effective value of this field is 1.
The counters affected by this field are:
Other event counters, PMCCNTR_EL0, and, if FEAT_PMUv3_ICNTR is implemented, PMICNTR_EL0 are not affected by this field.
The reset behavior of this field is:
Reserved, RES0.
Long cycle counter enable. Determines when unsigned overflow is recorded by the cycle counter overflow bit.
| LC | Meaning |
|---|---|
| 0b0 |
Cycle counter overflow on increment that causes unsigned overflow of PMCCNTR_EL0[31:0]. |
| 0b1 |
Cycle counter overflow on increment that causes unsigned overflow of PMCCNTR_EL0[63:0]. |
When FEAT_EBEP is implemented and the PMU exception is enabled, the Effective value of this field is 1.
Arm deprecates use of PMU.PMCR_EL0.LC = 0.
The reset behavior of this field is:
Reserved, RES1.
Disable cycle counter when event counting is prohibited.
| DP | Meaning |
|---|---|
| 0b0 |
Cycle counting by PMCCNTR_EL0 is not affected by this mechanism. |
| 0b1 | Cycle counting by PMCCNTR_EL0 is disabled in prohibited regions and when event counting is frozen:
|
The conditions when this field disables the cycle counter are the same as when event counting by an event counter PMEVCNTR<n>_EL0 is prohibited or frozen, when either EL2 is not implemented or n is less than MDCR_EL2.HPMN.
If FEAT_PMUv3p7 and FEAT_SPEv1p2 are implemented, meaning PMCR_EL0.FZS is implemented, and FEAT_SPE_DPFZS is not implemented, then cycle counting by PMCCNTR_EL0 is not affected by PMCR_EL0.FZS.
For more information, see 'Prohibiting event and cycle counting'.
The reset behavior of this field is:
Reserved, RES0.
Enable export of events in an IMPLEMENTATION DEFINED PMU event export bus.
| X | Meaning |
|---|---|
| 0b0 |
Do not export events. |
| 0b1 |
Export events where not prohibited. |
This field enables the exporting of events over an IMPLEMENTATION DEFINED PMU event export bus to another device, for example to an OPTIONAL trace unit.
No events are exported when counting is prohibited.
This field does not affect the generation of Performance Monitors overflow interrupt requests or signaling to a cross-trigger interface (CTI) that can be implemented as signals exported from the PE.
When this register has an architecturally-defined reset value, if this field is implemented as an RW field it resets to:
Reserved, RAZ/WI.
Clock divider.
| D | Meaning |
|---|---|
| 0b0 |
When enabled, PMCCNTR_EL0 counts every clock cycle. |
| 0b1 |
When enabled, PMCCNTR_EL0 counts once every 64 clock cycles. |
If PMCR_EL0.LC == 1, this bit is ignored and the cycle counter counts every clock cycle.
Arm deprecates use of PMCR_EL0.D = 1.
When this register has an architecturally-defined reset value, if this field is implemented as an RW field it resets to:
Reserved, RES0.
Cycle counter reset. The effects of writing to this bit are:
| C | Meaning |
|---|---|
| 0b0 |
No action. |
| 0b1 |
Reset PMCCNTR_EL0 to zero. |
Resetting PMCCNTR_EL0 does not change the cycle counter overflow bit. If FEAT_PMUv3p5 is implemented, the value of PMCR_EL0.LC is ignored, and bits [63:0] of the cycle counter are reset.
Access to this field is WO/RAZ.
Event counter reset. The effects of writing to this bit are:
| P | Meaning |
|---|---|
| 0b0 |
No action. |
| 0b1 |
Reset all event counters, not including PMCCNTR_EL0, to zero. |
Resetting the event counters does not change the event counter overflow bits. If FEAT_PMUv3p5 is implemented, the value of MDCR_EL2.HLP, or PMCR_EL0.LP is ignored and bits [63:0] of all affected event counters are reset.
Access to this field is WO/RAZ.
Enable.
In the description of this field:
| E | Meaning |
|---|---|
| 0b0 |
Affected counters are disabled and do not count. |
| 0b1 |
Affected counters are enabled by PMCNTENSET_EL0. |
The counters affected by this field are:
Other event counters are not affected by this field.
The reset behavior of this field is:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RAZ/WI | RES0 | FZO | RES0 | LP | LC | DP | X | D | C | P | E | ||||||||||||||||||||
Reserved, RAZ/WI.
Hardware must implement this field as RAZ/WI. Software must not rely on the register reading as zero, and must use a read-modify-write sequence to write to the register.
Reserved, RES0.
Freeze-on-overflow. Stop event counters on overflow.
In the description of this field:
| FZO | Meaning |
|---|---|
| 0b0 |
Do not freeze on overflow. |
| 0b1 | Affected counters do not count when any of the following applies:
|
The counters affected by this field are:
Other event counters are not affected by this field.
When PMCR_EL0.DP is 0, PMCCNTR_EL0 is not affected by this field.
The reset behavior of this field is:
Reserved, RES0.
Reserved, RES0.
Long event counter enable. Determines when unsigned overflow is recorded by an event counter overflow bit.
In the description of this field:
If EL2 is implemented and is using AArch32, then PMN is HDCR.HPMN.
If EL2 is implemented and is using AArch64, then PMN is MDCR_EL2.HPMN.
If EL2 is not implemented, then PMN is PMCR_EL0.N.
| LP | Meaning |
|---|---|
| 0b0 |
Event counter overflow on increment that causes unsigned overflow of PMEVCNTR<n>_EL0[31:0]. |
| 0b1 |
Event counter overflow on increment that causes unsigned overflow of PMEVCNTR<n>_EL0[63:0]. |
When FEAT_EBEP is implemented and the PMU exception is enabled, the Effective value of this field is 1.
The counters affected by this field are:
Other event counters, PMCCNTR_EL0, and, if FEAT_PMUv3_ICNTR is implemented, PMICNTR_EL0 are not affected by this field.
The reset behavior of this field is:
Reserved, RES0.
Long cycle counter enable. Determines when unsigned overflow is recorded by the cycle counter overflow bit.
| LC | Meaning |
|---|---|
| 0b0 |
Cycle counter overflow on increment that causes unsigned overflow of PMCCNTR_EL0[31:0]. |
| 0b1 |
Cycle counter overflow on increment that causes unsigned overflow of PMCCNTR_EL0[63:0]. |
When FEAT_EBEP is implemented and the PMU exception is enabled, the Effective value of this field is 1.
Arm deprecates use of PMU.PMCR_EL0.LC = 0.
The reset behavior of this field is:
Reserved, RES1.
Disable cycle counter when event counting is prohibited.
| DP | Meaning |
|---|---|
| 0b0 |
Cycle counting by PMCCNTR_EL0 is not affected by this mechanism. |
| 0b1 | Cycle counting by PMCCNTR_EL0 is disabled in prohibited regions and when event counting is frozen:
|
The conditions when this field disables the cycle counter are the same as when event counting by an event counter PMEVCNTR<n>_EL0 is prohibited or frozen, when either EL2 is not implemented or n is less than MDCR_EL2.HPMN.
If FEAT_PMUv3p7 and FEAT_SPEv1p2 are implemented, meaning PMCR_EL0.FZS is implemented, and FEAT_SPE_DPFZS is not implemented, then cycle counting by PMCCNTR_EL0 is not affected by PMCR_EL0.FZS.
For more information, see 'Prohibiting event and cycle counting'.
The reset behavior of this field is:
Reserved, RES0.
Enable export of events in an IMPLEMENTATION DEFINED PMU event export bus.
| X | Meaning |
|---|---|
| 0b0 |
Do not export events. |
| 0b1 |
Export events where not prohibited. |
This field enables the exporting of events over an IMPLEMENTATION DEFINED PMU event export bus to another device, for example to an OPTIONAL trace unit.
No events are exported when counting is prohibited.
This field does not affect the generation of Performance Monitors overflow interrupt requests or signaling to a cross-trigger interface (CTI) that can be implemented as signals exported from the PE.
When this register has an architecturally-defined reset value, if this field is implemented as an RW field it resets to:
Reserved, RAZ/WI.
Clock divider.
| D | Meaning |
|---|---|
| 0b0 |
When enabled, PMCCNTR_EL0 counts every clock cycle. |
| 0b1 |
When enabled, PMCCNTR_EL0 counts once every 64 clock cycles. |
If PMCR_EL0.LC == 1, this bit is ignored and the cycle counter counts every clock cycle.
Arm deprecates use of PMCR_EL0.D = 1.
When this register has an architecturally-defined reset value, if this field is implemented as an RW field it resets to:
Reserved, RES0.
Cycle counter reset. The effects of writing to this bit are:
| C | Meaning |
|---|---|
| 0b0 |
No action. |
| 0b1 |
Reset PMCCNTR_EL0 to zero. |
Resetting PMCCNTR_EL0 does not change the cycle counter overflow bit. If FEAT_PMUv3p5 is implemented, the value of PMCR_EL0.LC is ignored, and bits [63:0] of the cycle counter are reset.
Access to this field is WO/RAZ.
Event counter reset. The effects of writing to this bit are:
| P | Meaning |
|---|---|
| 0b0 |
No action. |
| 0b1 |
Reset all event counters, not including PMCCNTR_EL0, to zero. |
Resetting the event counters does not change the event counter overflow bits. If FEAT_PMUv3p5 is implemented, the value of MDCR_EL2.HLP, or PMCR_EL0.LP is ignored and bits [63:0] of all affected event counters are reset.
Access to this field is WO/RAZ.
Enable.
In the description of this field:
| E | Meaning |
|---|---|
| 0b0 |
Affected counters are disabled and do not count. |
| 0b1 |
Affected counters are enabled by PMCNTENSET_EL0. |
The counters affected by this field are:
Other event counters are not affected by this field.
The reset behavior of this field is:
SoftwareLockStatus() depends on the type of access attempted and AllowExternalPMUAccess() has a new definition from Armv8.4. Refer to the Pseudocode definitions for more information.
Accesses to this register use the following encodings:
Accessible at offset 0xE04 from PMU
Accessible at offset 0xE10 from PMU
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