ADCLT

Add with carry long (top)

Add the odd-numbered elements of the first source vector and the 1-bit carry from the least-significant bit of the odd-numbered elements of the second source vector to the even-numbered elements of the destination and accumulator vector. The 1-bit carry output is placed in the corresponding odd-numbered element of the destination vector.

313029282726252423222120191817161514131211109876543210
010001010sz0Zm110101ZnZda
T

ADCLT <Zda>.<T>, <Zn>.<T>, <Zm>.<T>

if !IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 32 << UInt(sz); constant integer n = UInt(Zn); constant integer m = UInt(Zm); constant integer da = UInt(Zda);

Assembler Symbols

<Zda>

Is the name of the third source and destination scalable vector register, encoded in the "Zda" field.

<T>

Is the size specifier, encoded in sz:

sz <T>
0 S
1 D
<Zn>

Is the name of the first source scalable vector register, encoded in the "Zn" field.

<Zm>

Is the name of the second source scalable vector register, encoded in the "Zm" field.

Operation

CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer pairs = VL DIV (esize * 2); constant bits(VL) operand = Z[n, VL]; constant bits(VL) carries = Z[m, VL]; bits(VL) result = Z[da, VL]; for p = 0 to pairs-1 constant bits(esize) element1 = Elem[result, 2*p + 0, esize]; constant bits(esize) element2 = Elem[operand, 2*p + 1, esize]; constant bit carry_in = Elem[carries, 2*p + 1, esize]<0>; (res, nzcv) = AddWithCarry(element1, element2, carry_in); carry_out = nzcv<1>; Elem[result, 2*p + 0, esize] = res; Elem[result, 2*p + 1, esize] = ZeroExtend(carry_out, esize); Z[da, VL] = result;

Operational information

If FEAT_SVE2 is implemented or FEAT_SME is implemented, then if PSTATE.DIT is 1:

This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is constrained unpredictable:


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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