Top-level encodings for A64

313029282726252423222120191817161514131211109876543210
op0op1
Decode fieldsInstruction details
op0op1
0 0000 Reserved
1 0000 SME encodings
0001 UNALLOCATED
0010 SVE encodings
0011 UNALLOCATED
100x Data Processing -- Immediate
101x Branches, Exception Generating and System instructions
x101 Data Processing -- Register
x111 Data Processing -- Scalar Floating-Point and Advanced SIMD
x1x0 Loads and Stores

Reserved

These instructions are under the top-level.

313029282726252423222120191817161514131211109876543210
0op00000op1
Decode fieldsInstruction details
op0op1
00 000000000 UDF
00 000000001 UNALLOCATED
00 00000001x UNALLOCATED
00 0000001xx UNALLOCATED
00 000001xxx UNALLOCATED
00 00001xxxx UNALLOCATED
00 0001xxxxx UNALLOCATED
00 001xxxxxx UNALLOCATED
00 01xxxxxxx UNALLOCATED
00 1xxxxxxxx UNALLOCATED
01 UNALLOCATED
1x UNALLOCATED

SME encodings

These instructions are under the top-level.

313029282726252423222120191817161514131211109876543210
1op00000op1op2
Decode fieldsInstruction details
op0op1op2
0x x10xxxxxxxxxxxx xx1x UNALLOCATED
0x x11xxxxxxxxxxxx x0xx SME Outer Product - 64 bit
0x x11xxxxxxxxxxxx x1xx UNALLOCATED
00 x0xxxxxxxxxxxxx UNALLOCATED
00 x10xxxxxxxxxxxx x00x SME FP Outer Product - 32 bit
00 x10xxxxxxxxxxxx x10x SME2 Outer Product - Misc
01 x10xxxxxxxxxxxx xx0x SME Integer Outer Product - 32 bit
01 00xxxxxxxxxxxxx SME2 Multi-vector - Memory (Contiguous)
01 10xxxxxxxxxxxxx SME2 Multi-vector - Memory (Strided)
10 0xx000x0xxxxxxx 0xxx SME Move into Array
10 0xx000x0xxxxxxx 1xxx UNALLOCATED
10 0xx000x1xxxxxxx SME Move from Array
10 0xx010xxxxxxxxx x0xx SME Add Vector to Array
10 0xx010xxxxxxxxx x1xx UNALLOCATED
10 0xx1xxxxxxxxxxx UNALLOCATED
10 00x011xxxxxxxxx UNALLOCATED
10 0000010xxxxxxxx SME Zero
10 0000011xxxxxxxx SME2 Multiple Zero
10 0010010xxxxxxxx SME2 Zero Lookup Table
10 0010011xxxxxxxx SME2 Move Lookup Table
10 01x001xxxxxxxxx SME2 Expand Lookup Table (Contiguous)
10 010011xxxxxxxxx SME2 Expand Lookup Table (Non-contiguous)
10 011011xxxxxxxxx UNALLOCATED
10 1xx00xxxxxxxxxx SME2 Multi-vector - Indexed (One register)
10 1xx01xxxx0xxxxx SME2 Multi-vector - Indexed (Two registers)
10 1xx01xxxx1xxxxx SME2 Multi-vector - Indexed (Four registers)
10 1xx1xxxxx100xxx SME2 Multi-vector - SVE Select
10 1xx1xxxxx110xxx SME2 Multi-vector - SVE Constructive Binary
10 1xx1xxxxx111000 SME2 Multi-vector - SVE Constructive Unary
10 1xx1xxxxx111001 UNALLOCATED
10 1xx1xxxxx11101x UNALLOCATED
10 1xx1xxxx0101100 SME2 Multi-vector - Multiple Vectors SVE Destructive (Two registers)
10 1xx1xxxx0101101 SME2 Multi-vector - Multiple Vectors SVE Saturating Multiply (Two registers)
10 1xx1xxx00101110 xxx0 SME2 Multi-vector - Multiple Vectors SVE Destructive (Four registers)
10 1xx1xxx00101111 xxx0 SME2 Multi-vector - Multiple Vectors SVE Saturating Multiply (Four registers)
10 1xx1xxx1010111x UNALLOCATED
10 1xx10xxxx10100x SME2 Multi-vector - Multiple and Single SVE Destructive (Two registers)
10 1xx10xxxx10101x xxx0 SME2 Multi-vector - Multiple and Single SVE Destructive (Four registers)
10 1xx10xxx01111xx UNALLOCATED
10 1xx10xxx11x11xx UNALLOCATED
10 1xx10xx00101x1x xxx1 UNALLOCATED
10 1xx10xx0110101x xxx1 UNALLOCATED
10 1xx10xx1x10101x xxx1 UNALLOCATED
10 1xx11xxxx1111xx UNALLOCATED
10 1xx11xxx01010xx UNALLOCATED
10 1xx11xxx1101xxx UNALLOCATED
10 1xx11xx0010111x xxx1 UNALLOCATED
10 10x10xxxx0xxxxx SME2 Multi-vector - Multiple and Single Array Vectors (Two registers)
10 10x11xxxx0xxxxx SME2 Multi-vector - Multiple and Single Array Vectors (Four registers)
10 11x1xxxx00xxxxx SME2 Multi-vector - Multiple Array Vectors (Two registers)
10 11x1xxxx10xxxxx SME2 Multi-vector - Multiple Array Vectors (Four registers)
11 SME Memory

SME Outer Product - 64 bit

These instructions are under SME encodings.

313029282726252423222120191817161514131211109876543210
10op00000op111op20
Decode fieldsInstruction details
op0op1op2
0 0 0 SME FP64 outer product
0 0 1 UNALLOCATED
0 1 UNALLOCATED
1 SME Int16 outer product

SME FP64 outer product

These instructions are under SME Outer Product - 64 bit.

313029282726252423222120191817161514131211109876543210
10000000110ZmPmPnZnS0ZAda
Decode fields Instruction Details Feature
S
0 FMOPA (non-widening)FEAT_SME_F64F64
1 FMOPS (non-widening)FEAT_SME_F64F64

SME Int16 outer product

These instructions are under SME Outer Product - 64 bit.

313029282726252423222120191817161514131211109876543210
1010000u011u1ZmPmPnZnS0ZAda
Decode fields Instruction Details Feature
u0 u1 S
0 0 0 SMOPA (4-way)FEAT_SME_I16I64
0 0 1 SMOPS (4-way)FEAT_SME_I16I64
0 1 0 SUMOPAFEAT_SME_I16I64
0 1 1 SUMOPSFEAT_SME_I16I64
1 0 0 USMOPAFEAT_SME_I16I64
1 0 1 USMOPSFEAT_SME_I16I64
1 1 0 UMOPA (4-way)FEAT_SME_I16I64
1 1 1 UMOPS (4-way)FEAT_SME_I16I64

SME FP Outer Product - 32 bit

These instructions are under SME encodings.

313029282726252423222120191817161514131211109876543210
1000000op010op1op200
Decode fieldsInstruction detailsFeature
op0op1op2
0 0 SME FP32 outer product-
0 1 0 FMOPA (widening, 4-way)FEAT_SME_F8F32
0 1 1 UNALLOCATED-
1 0 SME BF16 widening outer product-
1 1 SME FP16 widening outer product-

SME FP32 outer product

These instructions are under SME FP Outer Product - 32 bit.

313029282726252423222120191817161514131211109876543210
10000000100ZmPmPnZnS00ZAda
Decode fields Instruction Details Feature
S
0 FMOPA (non-widening)FEAT_SME
1 FMOPS (non-widening)FEAT_SME

SME BF16 widening outer product

These instructions are under SME FP Outer Product - 32 bit.

313029282726252423222120191817161514131211109876543210
10000001100ZmPmPnZnS00ZAda
Decode fields Instruction Details Feature
S
0 BFMOPA (widening)FEAT_SME
1 BFMOPS (widening)FEAT_SME

SME FP16 widening outer product

These instructions are under SME FP Outer Product - 32 bit.

313029282726252423222120191817161514131211109876543210
10000001101ZmPmPnZnS00ZAda
Decode fields Instruction Details Feature
S
0 FMOPA (widening, 2-way, FP16 to FP32)FEAT_SME
1 FMOPS (widening)FEAT_SME

SME2 Outer Product - Misc

These instructions are under SME encodings.

313029282726252423222120191817161514131211109876543210
1000000op010op1op210op3
Decode fieldsInstruction detailsFeature
op0op1op2op3
0 0 SME2 32-bit binary outer product-
0 1 0 0 FMOPA (widening, 2-way, FP8 to FP16)FEAT_SME_F8F16
0 1 0 1 UNALLOCATED-
0 1 1 UNALLOCATED-
1 0 0 SME2 FP16 non-widening outer product-
1 1 0 SME2 BF16 non-widening outer product-
1 1 UNALLOCATED-

SME2 32-bit binary outer product

These instructions are under SME2 Outer Product - Misc.

313029282726252423222120191817161514131211109876543210
10000000100ZmPmPnZnS10ZAda
Decode fields Instruction Details Feature
S
0 BMOPAFEAT_SME2
1 BMOPSFEAT_SME2

SME2 FP16 non-widening outer product

These instructions are under SME2 Outer Product - Misc.

313029282726252423222120191817161514131211109876543210
10000001100ZmPmPnZnS100ZAda
Decode fields Instruction Details Feature
S
0 FMOPA (non-widening)FEAT_SME_F16F16
1 FMOPS (non-widening)FEAT_SME_F16F16

SME2 BF16 non-widening outer product

These instructions are under SME2 Outer Product - Misc.

313029282726252423222120191817161514131211109876543210
10000001101ZmPmPnZnS100ZAda
Decode fields Instruction Details Feature
S
0 BFMOPA (non-widening)FEAT_SVE_B16B16
1 BFMOPS (non-widening)FEAT_SVE_B16B16

SME Integer Outer Product - 32 bit

These instructions are under SME encodings.

313029282726252423222120191817161514131211109876543210
101000010op0op10
Decode fieldsInstruction details
op0op1
0 1 SME2 Int16 two-way outer product
1 1 UNALLOCATED
0 SME Int8 outer product

SME2 Int16 two-way outer product

These instructions are under SME Integer Outer Product - 32 bit.

313029282726252423222120191817161514131211109876543210
1010000u0100ZmPmPnZnS10ZAda
Decode fields Instruction Details Feature
u0 S
0 0 SMOPA (2-way)FEAT_SME2
0 1 SMOPS (2-way)FEAT_SME2
1 0 UMOPA (2-way)FEAT_SME2
1 1 UMOPS (2-way)FEAT_SME2

SME Int8 outer product

These instructions are under SME Integer Outer Product - 32 bit.

313029282726252423222120191817161514131211109876543210
1010000u010u1ZmPmPnZnS00ZAda
Decode fields Instruction Details Feature
u0 u1 S
0 0 0 SMOPA (4-way)FEAT_SME
0 0 1 SMOPS (4-way)FEAT_SME
0 1 0 SUMOPAFEAT_SME
0 1 1 SUMOPSFEAT_SME
1 0 0 USMOPAFEAT_SME
1 0 1 USMOPSFEAT_SME
1 1 0 UMOPA (4-way)FEAT_SME
1 1 1 UMOPS (4-way)FEAT_SME

SME2 Multi-vector - Memory (Contiguous)

These instructions are under SME encodings.

313029282726252423222120191817161514131211109876543210
101000000op0op1op2
Decode fieldsInstruction details
op0op1op2
00x 0 SME2 multi-vec contiguous load (scalar plus scalar, two registers)
00x 1 0 SME2 multi-vec contiguous load (scalar plus scalar, four registers)
01x 0 SME2 multi-vec contiguous store (scalar plus scalar, two registers)
01x 1 0 SME2 multi-vec contiguous store (scalar plus scalar, four registers)
0xx 1 1 UNALLOCATED
100 0 SME2 multi-vec contiguous load (scalar plus immediate, two registers)
100 1 0 SME2 multi-vec contiguous load (scalar plus immediate, four registers)
110 0 SME2 multi-vec contiguous store (scalar plus immediate, two registers)
110 1 0 SME2 multi-vec contiguous store (scalar plus immediate, four registers)
1x0 1 1 UNALLOCATED
1x1 UNALLOCATED

SME2 multi-vec contiguous load (scalar plus scalar, two registers)

These instructions are under SME2 Multi-vector - Memory (Contiguous).

313029282726252423222120191817161514131211109876543210
10100000000Rm0mszPNgRnZtN
Decode fields Instruction Details Feature
msz N
00 0 LD1B (scalar plus scalar, consecutive registers)FEAT_SVE2p1
00 1 LDNT1B (scalar plus scalar, consecutive registers)FEAT_SVE2p1
01 0 LD1H (scalar plus scalar, consecutive registers)FEAT_SVE2p1
01 1 LDNT1H (scalar plus scalar, consecutive registers)FEAT_SVE2p1
10 0 LD1W (scalar plus scalar, consecutive registers)FEAT_SVE2p1
10 1 LDNT1W (scalar plus scalar, consecutive registers)FEAT_SVE2p1
11 0 LD1D (scalar plus scalar, consecutive registers)FEAT_SVE2p1
11 1 LDNT1D (scalar plus scalar, consecutive registers)FEAT_SVE2p1

SME2 multi-vec contiguous load (scalar plus scalar, four registers)

These instructions are under SME2 Multi-vector - Memory (Contiguous).

313029282726252423222120191817161514131211109876543210
10100000000Rm1mszPNgRnZt0N
Decode fields Instruction Details Feature
msz N
00 0 LD1B (scalar plus scalar, consecutive registers)FEAT_SVE2p1
00 1 LDNT1B (scalar plus scalar, consecutive registers)FEAT_SVE2p1
01 0 LD1H (scalar plus scalar, consecutive registers)FEAT_SVE2p1
01 1 LDNT1H (scalar plus scalar, consecutive registers)FEAT_SVE2p1
10 0 LD1W (scalar plus scalar, consecutive registers)FEAT_SVE2p1
10 1 LDNT1W (scalar plus scalar, consecutive registers)FEAT_SVE2p1
11 0 LD1D (scalar plus scalar, consecutive registers)FEAT_SVE2p1
11 1 LDNT1D (scalar plus scalar, consecutive registers)FEAT_SVE2p1

SME2 multi-vec contiguous store (scalar plus scalar, two registers)

These instructions are under SME2 Multi-vector - Memory (Contiguous).

313029282726252423222120191817161514131211109876543210
10100000001Rm0mszPNgRnZtN
Decode fields Instruction Details Feature
msz N
00 0 ST1B (scalar plus scalar, consecutive registers)FEAT_SVE2p1
00 1 STNT1B (scalar plus scalar, consecutive registers)FEAT_SVE2p1
01 0 ST1H (scalar plus scalar, consecutive registers)FEAT_SVE2p1
01 1 STNT1H (scalar plus scalar, consecutive registers)FEAT_SVE2p1
10 0 ST1W (scalar plus scalar, consecutive registers)FEAT_SVE2p1
10 1 STNT1W (scalar plus scalar, consecutive registers)FEAT_SVE2p1
11 0 ST1D (scalar plus scalar, consecutive registers)FEAT_SVE2p1
11 1 STNT1D (scalar plus scalar, consecutive registers)FEAT_SVE2p1

SME2 multi-vec contiguous store (scalar plus scalar, four registers)

These instructions are under SME2 Multi-vector - Memory (Contiguous).

313029282726252423222120191817161514131211109876543210
10100000001Rm1mszPNgRnZt0N
Decode fields Instruction Details Feature
msz N
00 0 ST1B (scalar plus scalar, consecutive registers)FEAT_SVE2p1
00 1 STNT1B (scalar plus scalar, consecutive registers)FEAT_SVE2p1
01 0 ST1H (scalar plus scalar, consecutive registers)FEAT_SVE2p1
01 1 STNT1H (scalar plus scalar, consecutive registers)FEAT_SVE2p1
10 0 ST1W (scalar plus scalar, consecutive registers)FEAT_SVE2p1
10 1 STNT1W (scalar plus scalar, consecutive registers)FEAT_SVE2p1
11 0 ST1D (scalar plus scalar, consecutive registers)FEAT_SVE2p1
11 1 STNT1D (scalar plus scalar, consecutive registers)FEAT_SVE2p1

SME2 multi-vec contiguous load (scalar plus immediate, two registers)

These instructions are under SME2 Multi-vector - Memory (Contiguous).

313029282726252423222120191817161514131211109876543210
101000000100imm40mszPNgRnZtN
Decode fields Instruction Details Feature
msz N
00 0 LD1B (scalar plus immediate, consecutive registers)FEAT_SVE2p1
00 1 LDNT1B (scalar plus immediate, consecutive registers)FEAT_SVE2p1
01 0 LD1H (scalar plus immediate, consecutive registers)FEAT_SVE2p1
01 1 LDNT1H (scalar plus immediate, consecutive registers)FEAT_SVE2p1
10 0 LD1W (scalar plus immediate, consecutive registers)FEAT_SVE2p1
10 1 LDNT1W (scalar plus immediate, consecutive registers)FEAT_SVE2p1
11 0 LD1D (scalar plus immediate, consecutive registers)FEAT_SVE2p1
11 1 LDNT1D (scalar plus immediate, consecutive registers)FEAT_SVE2p1

SME2 multi-vec contiguous load (scalar plus immediate, four registers)

These instructions are under SME2 Multi-vector - Memory (Contiguous).

313029282726252423222120191817161514131211109876543210
101000000100imm41mszPNgRnZt0N
Decode fields Instruction Details Feature
msz N
00 0 LD1B (scalar plus immediate, consecutive registers)FEAT_SVE2p1
00 1 LDNT1B (scalar plus immediate, consecutive registers)FEAT_SVE2p1
01 0 LD1H (scalar plus immediate, consecutive registers)FEAT_SVE2p1
01 1 LDNT1H (scalar plus immediate, consecutive registers)FEAT_SVE2p1
10 0 LD1W (scalar plus immediate, consecutive registers)FEAT_SVE2p1
10 1 LDNT1W (scalar plus immediate, consecutive registers)FEAT_SVE2p1
11 0 LD1D (scalar plus immediate, consecutive registers)FEAT_SVE2p1
11 1 LDNT1D (scalar plus immediate, consecutive registers)FEAT_SVE2p1

SME2 multi-vec contiguous store (scalar plus immediate, two registers)

These instructions are under SME2 Multi-vector - Memory (Contiguous).

313029282726252423222120191817161514131211109876543210
101000000110imm40mszPNgRnZtN
Decode fields Instruction Details Feature
msz N
00 0 ST1B (scalar plus immediate, consecutive registers)FEAT_SVE2p1
00 1 STNT1B (scalar plus immediate, consecutive registers)FEAT_SVE2p1
01 0 ST1H (scalar plus immediate, consecutive registers)FEAT_SVE2p1
01 1 STNT1H (scalar plus immediate, consecutive registers)FEAT_SVE2p1
10 0 ST1W (scalar plus immediate, consecutive registers)FEAT_SVE2p1
10 1 STNT1W (scalar plus immediate, consecutive registers)FEAT_SVE2p1
11 0 ST1D (scalar plus immediate, consecutive registers)FEAT_SVE2p1
11 1 STNT1D (scalar plus immediate, consecutive registers)FEAT_SVE2p1

SME2 multi-vec contiguous store (scalar plus immediate, four registers)

These instructions are under SME2 Multi-vector - Memory (Contiguous).

313029282726252423222120191817161514131211109876543210
101000000110imm41mszPNgRnZt0N
Decode fields Instruction Details Feature
msz N
00 0 ST1B (scalar plus immediate, consecutive registers)FEAT_SVE2p1
00 1 STNT1B (scalar plus immediate, consecutive registers)FEAT_SVE2p1
01 0 ST1H (scalar plus immediate, consecutive registers)FEAT_SVE2p1
01 1 STNT1H (scalar plus immediate, consecutive registers)FEAT_SVE2p1
10 0 ST1W (scalar plus immediate, consecutive registers)FEAT_SVE2p1
10 1 STNT1W (scalar plus immediate, consecutive registers)FEAT_SVE2p1
11 0 ST1D (scalar plus immediate, consecutive registers)FEAT_SVE2p1
11 1 STNT1D (scalar plus immediate, consecutive registers)FEAT_SVE2p1

SME2 Multi-vector - Memory (Strided)

These instructions are under SME encodings.

313029282726252423222120191817161514131211109876543210
101000010op0op1op2
Decode fieldsInstruction details
op0op1op2
00x 0 SME2 multi-vec non-contiguous load (scalar plus scalar, two registers)
00x 1 0 SME2 multi-vec non-contiguous load (scalar plus scalar, four registers)
01x 0 SME2 multi-vec non-contiguous store (scalar plus scalar, two registers)
01x 1 0 SME2 multi-vec non-contiguous store (scalar plus scalar, four registers)
0xx 1 1 UNALLOCATED
100 0 SME2 multi-vec non-contiguous load (scalar plus immediate, two registers)
100 1 0 SME2 multi-vec non-contiguous load (scalar plus immediate, four registers)
110 0 SME2 multi-vec non-contiguous store (scalar plus immediate, two registers)
110 1 0 SME2 multi-vec non-contiguous store (scalar plus immediate, four registers)
1x0 1 1 UNALLOCATED
1x1 UNALLOCATED

SME2 multi-vec non-contiguous load (scalar plus scalar, two registers)

These instructions are under SME2 Multi-vector - Memory (Strided).

313029282726252423222120191817161514131211109876543210
10100001000Rm0mszPNgRnZthNZtl
Decode fields Instruction Details Feature
msz N
00 0 LD1B (scalar plus scalar, strided registers)FEAT_SME2
00 1 LDNT1B (scalar plus scalar, strided registers)FEAT_SME2
01 0 LD1H (scalar plus scalar, strided registers)FEAT_SME2
01 1 LDNT1H (scalar plus scalar, strided registers)FEAT_SME2
10 0 LD1W (scalar plus scalar, strided registers)FEAT_SME2
10 1 LDNT1W (scalar plus scalar, strided registers)FEAT_SME2
11 0 LD1D (scalar plus scalar, strided registers)FEAT_SME2
11 1 LDNT1D (scalar plus scalar, strided registers)FEAT_SME2

SME2 multi-vec non-contiguous load (scalar plus scalar, four registers)

These instructions are under SME2 Multi-vector - Memory (Strided).

313029282726252423222120191817161514131211109876543210
10100001000Rm1mszPNgRnZthN0Ztl
Decode fields Instruction Details Feature
msz N
00 0 LD1B (scalar plus scalar, strided registers)FEAT_SME2
00 1 LDNT1B (scalar plus scalar, strided registers)FEAT_SME2
01 0 LD1H (scalar plus scalar, strided registers)FEAT_SME2
01 1 LDNT1H (scalar plus scalar, strided registers)FEAT_SME2
10 0 LD1W (scalar plus scalar, strided registers)FEAT_SME2
10 1 LDNT1W (scalar plus scalar, strided registers)FEAT_SME2
11 0 LD1D (scalar plus scalar, strided registers)FEAT_SME2
11 1 LDNT1D (scalar plus scalar, strided registers)FEAT_SME2

SME2 multi-vec non-contiguous store (scalar plus scalar, two registers)

These instructions are under SME2 Multi-vector - Memory (Strided).

313029282726252423222120191817161514131211109876543210
10100001001Rm0mszPNgRnZthNZtl
Decode fields Instruction Details Feature
msz N
00 0 ST1B (scalar plus scalar, strided registers)FEAT_SME2
00 1 STNT1B (scalar plus scalar, strided registers)FEAT_SME2
01 0 ST1H (scalar plus scalar, strided registers)FEAT_SME2
01 1 STNT1H (scalar plus scalar, strided registers)FEAT_SME2
10 0 ST1W (scalar plus scalar, strided registers)FEAT_SME2
10 1 STNT1W (scalar plus scalar, strided registers)FEAT_SME2
11 0 ST1D (scalar plus scalar, strided registers)FEAT_SME2
11 1 STNT1D (scalar plus scalar, strided registers)FEAT_SME2

SME2 multi-vec non-contiguous store (scalar plus scalar, four registers)

These instructions are under SME2 Multi-vector - Memory (Strided).

313029282726252423222120191817161514131211109876543210
10100001001Rm1mszPNgRnZthN0Ztl
Decode fields Instruction Details Feature
msz N
00 0 ST1B (scalar plus scalar, strided registers)FEAT_SME2
00 1 STNT1B (scalar plus scalar, strided registers)FEAT_SME2
01 0 ST1H (scalar plus scalar, strided registers)FEAT_SME2
01 1 STNT1H (scalar plus scalar, strided registers)FEAT_SME2
10 0 ST1W (scalar plus scalar, strided registers)FEAT_SME2
10 1 STNT1W (scalar plus scalar, strided registers)FEAT_SME2
11 0 ST1D (scalar plus scalar, strided registers)FEAT_SME2
11 1 STNT1D (scalar plus scalar, strided registers)FEAT_SME2

SME2 multi-vec non-contiguous load (scalar plus immediate, two registers)

These instructions are under SME2 Multi-vector - Memory (Strided).

313029282726252423222120191817161514131211109876543210
101000010100imm40mszPNgRnZthNZtl
Decode fields Instruction Details Feature
msz N
00 0 LD1B (scalar plus immediate, strided registers)FEAT_SME2
00 1 LDNT1B (scalar plus immediate, strided registers)FEAT_SME2
01 0 LD1H (scalar plus immediate, strided registers)FEAT_SME2
01 1 LDNT1H (scalar plus immediate, strided registers)FEAT_SME2
10 0 LD1W (scalar plus immediate, strided registers)FEAT_SME2
10 1 LDNT1W (scalar plus immediate, strided registers)FEAT_SME2
11 0 LD1D (scalar plus immediate, strided registers)FEAT_SME2
11 1 LDNT1D (scalar plus immediate, strided registers)FEAT_SME2

SME2 multi-vec non-contiguous load (scalar plus immediate, four registers)

These instructions are under SME2 Multi-vector - Memory (Strided).

313029282726252423222120191817161514131211109876543210
101000010100imm41mszPNgRnZthN0Ztl
Decode fields Instruction Details Feature
msz N
00 0 LD1B (scalar plus immediate, strided registers)FEAT_SME2
00 1 LDNT1B (scalar plus immediate, strided registers)FEAT_SME2
01 0 LD1H (scalar plus immediate, strided registers)FEAT_SME2
01 1 LDNT1H (scalar plus immediate, strided registers)FEAT_SME2
10 0 LD1W (scalar plus immediate, strided registers)FEAT_SME2
10 1 LDNT1W (scalar plus immediate, strided registers)FEAT_SME2
11 0 LD1D (scalar plus immediate, strided registers)FEAT_SME2
11 1 LDNT1D (scalar plus immediate, strided registers)FEAT_SME2

SME2 multi-vec non-contiguous store (scalar plus immediate, two registers)

These instructions are under SME2 Multi-vector - Memory (Strided).

313029282726252423222120191817161514131211109876543210
101000010110imm40mszPNgRnZthNZtl
Decode fields Instruction Details Feature
msz N
00 0 ST1B (scalar plus immediate, strided registers)FEAT_SME2
00 1 STNT1B (scalar plus immediate, strided registers)FEAT_SME2
01 0 ST1H (scalar plus immediate, strided registers)FEAT_SME2
01 1 STNT1H (scalar plus immediate, strided registers)FEAT_SME2
10 0 ST1W (scalar plus immediate, strided registers)FEAT_SME2
10 1 STNT1W (scalar plus immediate, strided registers)FEAT_SME2
11 0 ST1D (scalar plus immediate, strided registers)FEAT_SME2
11 1 STNT1D (scalar plus immediate, strided registers)FEAT_SME2

SME2 multi-vec non-contiguous store (scalar plus immediate, four registers)

These instructions are under SME2 Multi-vector - Memory (Strided).

313029282726252423222120191817161514131211109876543210
101000010110imm41mszPNgRnZthN0Ztl
Decode fields Instruction Details Feature
msz N
00 0 ST1B (scalar plus immediate, strided registers)FEAT_SME2
00 1 STNT1B (scalar plus immediate, strided registers)FEAT_SME2
01 0 ST1H (scalar plus immediate, strided registers)FEAT_SME2
01 1 STNT1H (scalar plus immediate, strided registers)FEAT_SME2
10 0 ST1W (scalar plus immediate, strided registers)FEAT_SME2
10 1 STNT1W (scalar plus immediate, strided registers)FEAT_SME2
11 0 ST1D (scalar plus immediate, strided registers)FEAT_SME2
11 1 STNT1D (scalar plus immediate, strided registers)FEAT_SME2

SME Move into Array

These instructions are under SME encodings.

313029282726252423222120191817161514131211109876543210
11000000op0000op10op2op3op40op5
Decode fieldsInstruction detailsFeature
op0op1op2op3op4op5
00 1 00 010 x0 0 MOVA (vector to array, two registers)FEAT_SME2
00 1 00 011 00 0 MOVA (vector to array, four registers)FEAT_SME2
00 1 00 0x0 x0 1 UNALLOCATED-
00 1 00 0x0 x1 UNALLOCATED-
00 1 00 0x1 00 1 UNALLOCATED-
00 1 00 0x1 != 00 UNALLOCATED-
00 1 01 000 x0 1 UNALLOCATED-
00 1 01 000 x1 UNALLOCATED-
00 1 01 001 00 1 UNALLOCATED-
00 1 01 001 != 00 UNALLOCATED-
00 1 01 01x UNALLOCATED-
!= 00 1 0x 000 x0 1 UNALLOCATED-
!= 00 1 0x 000 x1 UNALLOCATED-
!= 00 1 0x 001 00 1 UNALLOCATED-
!= 00 1 0x 001 01 UNALLOCATED-
!= 00 1 0x 001 1x UNALLOCATED-
!= 00 1 0x 01x UNALLOCATED-
0 SME move vector to array-
1 0x 000 x0 0 SME2 move vector to tile, two registers-
1 0x 001 00 0 SME2 move vector to tile, four registers-
1 0x 1xx UNALLOCATED-
1 1x UNALLOCATED-

SME move vector to array

These instructions are under SME Move into Array.

313029282726252423222120191817161514131211109876543210
11000000size00000QVRsPgZn0opc
Decode fields Instruction Details Feature
size Q
0x 1 UNALLOCATED-
00 0 MOVA (vector to tile, single)8-bitFEAT_SME
01 0 MOVA (vector to tile, single)16-bitFEAT_SME
10 0 MOVA (vector to tile, single)32-bitFEAT_SME
10 1 UNALLOCATED-
11 0 MOVA (vector to tile, single)64-bitFEAT_SME
11 1 MOVA (vector to tile, single)128-bitFEAT_SME

SME2 move vector to tile, two registers

These instructions are under SME Move into Array.

313029282726252423222120191817161514131211109876543210
11000000size000100VRs000Zn000opc
Decode fields Instruction Details Feature
size
00 MOVA (vector to tile, two registers)8-bitFEAT_SME2
01 MOVA (vector to tile, two registers)16-bitFEAT_SME2
10 MOVA (vector to tile, two registers)32-bitFEAT_SME2
11 MOVA (vector to tile, two registers)64-bitFEAT_SME2

SME2 move vector to tile, four registers

These instructions are under SME Move into Array.

313029282726252423222120191817161514131211109876543210
11000000size000100VRs001Zn0000opc
Decode fields Instruction Details Feature
size opc
0x 1xx UNALLOCATED-
00 0xx MOVA (vector to tile, four registers)8-bitFEAT_SME2
01 0xx MOVA (vector to tile, four registers)16-bitFEAT_SME2
10 0xx MOVA (vector to tile, four registers)32-bitFEAT_SME2
10 1xx UNALLOCATED-
11 MOVA (vector to tile, four registers)64-bitFEAT_SME2

SME Move from Array

These instructions are under SME encodings.

313029282726252423222120191817161514131211109876543210
11000000op0000op11op2op3op4op5
Decode fieldsInstruction detailsFeature
op0op1op2op3op4op5
00 1 00 010 00 x0 MOVA (array to vector, two registers)FEAT_SME2
00 1 00 010 10 x0 MOVAZ (array to vector, two registers)FEAT_SME2p1
00 1 00 011 00 00 MOVA (array to vector, four registers)FEAT_SME2
00 1 00 011 10 00 MOVAZ (array to vector, four registers)FEAT_SME2p1
00 1 00 0x0 x0 x1 UNALLOCATED-
00 1 00 0x1 x0 != 00 UNALLOCATED-
00 1 00 0xx x1 UNALLOCATED-
00 1 01 000 x0 x1 UNALLOCATED-
00 1 01 001 x0 != 00 UNALLOCATED-
00 1 01 00x x1 UNALLOCATED-
00 1 01 01x UNALLOCATED-
!= 00 1 0x 000 x0 x1 UNALLOCATED-
!= 00 1 0x 001 x0 01 UNALLOCATED-
!= 00 1 0x 001 x0 1x UNALLOCATED-
!= 00 1 0x 00x x1 UNALLOCATED-
!= 00 1 0x 01x UNALLOCATED-
0 000 1x SME zeroing move array to vector-
0 != 000 1x UNALLOCATED-
0 0x SME move array to vector-
1 0x 000 00 x0 SME2 move tile to vector, two registers-
1 0x 000 10 x0 SME2 zeroing move tile to vector, two registers-
1 0x 001 00 00 SME2 move tile to vector, four registers-
1 0x 001 10 00 SME2 zeroing move tile to vector, four registers-
1 0x 1xx UNALLOCATED-
1 1x UNALLOCATED-

SME zeroing move array to vector

These instructions are under SME Move from Array.

313029282726252423222120191817161514131211109876543210
11000000size00001QVRs0001opcZd
Decode fields Instruction Details Feature
size Q
0x 1 UNALLOCATED-
00 0 MOVAZ (tile to vector, single)8-bitFEAT_SME2p1
01 0 MOVAZ (tile to vector, single)16-bitFEAT_SME2p1
10 0 MOVAZ (tile to vector, single)32-bitFEAT_SME2p1
10 1 UNALLOCATED-
11 0 MOVAZ (tile to vector, single)64-bitFEAT_SME2p1
11 1 MOVAZ (tile to vector, single)128-bitFEAT_SME2p1

SME move array to vector

These instructions are under SME Move from Array.

313029282726252423222120191817161514131211109876543210
11000000size00001QVRsPg0opcZd
Decode fields Instruction Details Feature
size Q
0x 1 UNALLOCATED-
00 0 MOVA (tile to vector, single)8-bitFEAT_SME
01 0 MOVA (tile to vector, single)16-bitFEAT_SME
10 0 MOVA (tile to vector, single)32-bitFEAT_SME
10 1 UNALLOCATED-
11 0 MOVA (tile to vector, single)64-bitFEAT_SME
11 1 MOVA (tile to vector, single)128-bitFEAT_SME

SME2 move tile to vector, two registers

These instructions are under SME Move from Array.

313029282726252423222120191817161514131211109876543210
11000000size000110VRs00000opcZd0
Decode fields Instruction Details Feature
size
00 MOVA (tile to vector, two registers)8-bitFEAT_SME2
01 MOVA (tile to vector, two registers)16-bitFEAT_SME2
10 MOVA (tile to vector, two registers)32-bitFEAT_SME2
11 MOVA (tile to vector, two registers)64-bitFEAT_SME2

SME2 zeroing move tile to vector, two registers

These instructions are under SME Move from Array.

313029282726252423222120191817161514131211109876543210
11000000size000110VRs00010opcZd0
Decode fields Instruction Details Feature
size
00 MOVAZ (tile to vector, two registers)8-bitFEAT_SME2p1
01 MOVAZ (tile to vector, two registers)16-bitFEAT_SME2p1
10 MOVAZ (tile to vector, two registers)32-bitFEAT_SME2p1
11 MOVAZ (tile to vector, two registers)64-bitFEAT_SME2p1

SME2 move tile to vector, four registers

These instructions are under SME Move from Array.

313029282726252423222120191817161514131211109876543210
11000000size000110VRs00100opcZd00
Decode fields Instruction Details Feature
size opc
0x 1xx UNALLOCATED-
00 0xx MOVA (tile to vector, four registers)8-bitFEAT_SME2
01 0xx MOVA (tile to vector, four registers)16-bitFEAT_SME2
10 0xx MOVA (tile to vector, four registers)32-bitFEAT_SME2
10 1xx UNALLOCATED-
11 MOVA (tile to vector, four registers)64-bitFEAT_SME2

SME2 zeroing move tile to vector, four registers

These instructions are under SME Move from Array.

313029282726252423222120191817161514131211109876543210
11000000size000110VRs00110opcZd00
Decode fields Instruction Details Feature
size opc
0x 1xx UNALLOCATED-
00 0xx MOVAZ (tile to vector, four registers)8-bitFEAT_SME2p1
01 0xx MOVAZ (tile to vector, four registers)16-bitFEAT_SME2p1
10 0xx MOVAZ (tile to vector, four registers)32-bitFEAT_SME2p1
10 1xx UNALLOCATED-
11 MOVAZ (tile to vector, four registers)64-bitFEAT_SME2p1

SME Add Vector to Array

These instructions are under SME encodings.

313029282726252423222120191817161514131211109876543210
11000000op0010op1op20
Decode fieldsInstruction details
op0op1op2
0 UNALLOCATED
1 00 0 SME add vector to array
1 00 1 UNALLOCATED
1 != 00 UNALLOCATED

SME add vector to array

These instructions are under SME Add Vector to Array.

313029282726252423222120191817161514131211109876543210
110000001op01000VPmPnZn00opc2
Decode fields Instruction Details Feature
op V opc2
0 1xx UNALLOCATED-
0 0 0xx ADDHA32-bitFEAT_SME
0 1 0xx ADDVA32-bitFEAT_SME
1 0 ADDHA64-bitFEAT_SME_I16I64
1 1 ADDVA64-bitFEAT_SME_I16I64

SME Zero

These instructions are under SME encodings.

313029282726252423222120191817161514131211109876543210
11000000000010op0
Decode fieldsInstruction detailsFeature
op0
0000000000 ZERO (tiles)FEAT_SME
!= 0000000000 UNALLOCATED-

SME2 Multiple Zero

These instructions are under SME encodings.

313029282726252423222120191817161514131211109876543210
11000000000011op0
Decode fieldsInstruction details
op0
0000000000 SME multiple vectors zero array
!= 0000000000 UNALLOCATED

SME multiple vectors zero array

These instructions are under SME2 Multiple Zero.

313029282726252423222120191817161514131211109876543210
11000000000011opcRv0000000000opc2
Decode fields Instruction Details Feature
opc opc2
x1x 1xx UNALLOCATED-
000 ZERO (single-vector)two ZA single-vectorsFEAT_SME2p1
001 ZERO (double-vector)one ZA double-vectorFEAT_SME2p1
010 0xx ZERO (double-vector)two ZA double-vectorsFEAT_SME2p1
011 0xx ZERO (double-vector)four ZA double-vectorsFEAT_SME2p1
100 ZERO (single-vector)four ZA single-vectorsFEAT_SME2p1
101 0xx ZERO (quad-vector)one ZA quad-vectorFEAT_SME2p1
101 1xx UNALLOCATED-
11x 01x UNALLOCATED-
110 00x ZERO (quad-vector)two ZA quad-vectorsFEAT_SME2p1
111 00x ZERO (quad-vector)four ZA quad-vectorsFEAT_SME2p1

SME2 Zero Lookup Table

These instructions are under SME encodings.

313029282726252423222120191817161514131211109876543210
11000000010010op0
Decode fieldsInstruction details
op0
00000000000000 SME2 zero lookup table
!= 00000000000000 UNALLOCATED

SME2 zero lookup table

These instructions are under SME encodings.

313029282726252423222120191817161514131211109876543210
1100000001001000000000000000opc
Decode fields Instruction Details Feature
opc
0000 UNALLOCATED-
0001 ZERO (table)FEAT_SME2
001x UNALLOCATED-
01xx UNALLOCATED-
1xxx UNALLOCATED-

SME2 zero lookup table

These instructions are under SME2 Zero Lookup Table.

313029282726252423222120191817161514131211109876543210
1100000001001000000000000000opc
Decode fields Instruction Details Feature
opc
0000 UNALLOCATED-
0001 ZERO (table)FEAT_SME2
001x UNALLOCATED-
01xx UNALLOCATED-
1xxx UNALLOCATED-

SME2 Move Lookup Table

These instructions are under SME encodings.

313029282726252423222120191817161514131211109876543210
11000000010011op0op1op2
Decode fieldsInstruction details
op0op1op2
0 00 SME2 move from lookup table
0 != 00 UNALLOCATED
1 00 SME2 move into lookup table
1 10 0 SME2 move vector to lookup table
1 10 1 UNALLOCATED
1 x1 UNALLOCATED

SME2 move from lookup table

These instructions are under SME2 Move Lookup Table.

313029282726252423222120191817161514131211109876543210
11000000010011000imm3opcRt
Decode fields Instruction Details Feature
opc
000xxxx UNALLOCATED-
0010xxx UNALLOCATED-
00110xx UNALLOCATED-
001110x UNALLOCATED-
0011110 UNALLOCATED-
0011111 MOVT (table to scalar)FEAT_SME2
01xxxxx UNALLOCATED-
1xxxxxx UNALLOCATED-

SME2 move into lookup table

These instructions are under SME2 Move Lookup Table.

313029282726252423222120191817161514131211109876543210
11000000010011100imm3opcRt
Decode fields Instruction Details Feature
opc
000xxxx UNALLOCATED-
0010xxx UNALLOCATED-
00110xx UNALLOCATED-
001110x UNALLOCATED-
0011110 UNALLOCATED-
0011111 MOVT (scalar to table)FEAT_SME2
01xxxxx UNALLOCATED-
1xxxxxx UNALLOCATED-

SME2 move vector to lookup table

These instructions are under SME2 Move Lookup Table.

313029282726252423222120191817161514131211109876543210
110000000100111100off2opcZt
Decode fields Instruction Details Feature
opc
000xxxx UNALLOCATED-
0010xxx UNALLOCATED-
00110xx UNALLOCATED-
001110x UNALLOCATED-
0011110 UNALLOCATED-
0011111 MOVT (vector to table)FEAT_SME_LUTv2
01xxxxx UNALLOCATED-
1xxxxxx UNALLOCATED-

SME2 Expand Lookup Table (Contiguous)

These instructions are under SME encodings.

313029282726252423222120191817161514131211109876543210
110000001op0001op1op2op3
Decode fieldsInstruction details
op0op1op2op3
0 00x00 UNALLOCATED
0 01000 UNALLOCATED
0 01100 0 00 SME2 lookup table two source registers expand to four contiguous destination registers
0 01100 0 != 00 UNALLOCATED
0 01100 1 UNALLOCATED
0 1xx00 UNALLOCATED
0 xxx10 00 SME2 lookup table expand four contiguous registers
0 xxx10 != 00 UNALLOCATED
0 xxxx1 x0 SME2 lookup table expand two contiguous registers
0 xxxx1 x1 UNALLOCATED
1 SME2 lookup table expand one register

SME2 lookup table two source registers expand to four contiguous destination registers

These instructions are under SME2 Expand Lookup Table (Contiguous).

313029282726252423222120191817161514131211109876543210
110000001000101100sizeopcZn0Zd00
Decode fields Instruction Details Feature
opc
00 LUTI4 (four registers, 8-bit)FEAT_SME_LUTv2
01 UNALLOCATED-
1x UNALLOCATED-

SME2 lookup table expand four contiguous registers

These instructions are under SME2 Expand Lookup Table (Contiguous).

313029282726252423222120191817161514131211109876543210
1100000010001opc10sizeopc2ZnZd00
Decode fields Instruction Details Feature
opc opc2
00x UNALLOCATED-
01x 00 LUTI4 (four registers, 16-bit & 32-bit)FEAT_SME2
01x 01 UNALLOCATED-
01x 1x UNALLOCATED-
1xx 00 LUTI2 (four registers)FEAT_SME2
1xx 01 UNALLOCATED-
1xx 1x UNALLOCATED-

SME2 lookup table expand two contiguous registers

These instructions are under SME2 Expand Lookup Table (Contiguous).

313029282726252423222120191817161514131211109876543210
1100000010001opc1sizeopc2ZnZd0
Decode fields Instruction Details Feature
opc opc2
00xx UNALLOCATED-
01xx 00 LUTI4 (two registers)FEAT_SME2
01xx 01 UNALLOCATED-
01xx 1x UNALLOCATED-
1xxx 00 LUTI2 (two registers)FEAT_SME2
1xxx 01 UNALLOCATED-
1xxx 1x UNALLOCATED-

SME2 lookup table expand one register

These instructions are under SME2 Expand Lookup Table (Contiguous).

313029282726252423222120191817161514131211109876543210
1100000011001opcsizeopc2ZnZd
Decode fields Instruction Details Feature
opc opc2
00xxx UNALLOCATED-
01xxx 00 LUTI4 (single)FEAT_SME2
01xxx 01 UNALLOCATED-
01xxx 1x UNALLOCATED-
1xxxx 00 LUTI2 (single)FEAT_SME2
1xxxx 01 UNALLOCATED-
1xxxx 1x UNALLOCATED-

SME2 Expand Lookup Table (Non-contiguous)

These instructions are under SME encodings.

313029282726252423222120191817161514131211109876543210
1100000010011op0op1op2op3
Decode fieldsInstruction details
op0op1op2op3
00x 00 UNALLOCATED
010 00 UNALLOCATED
011 00 0 00 SME2 lookup table two source registers expand to four non-contiguous destination registers
011 00 0 != 00 UNALLOCATED
011 00 1 UNALLOCATED
1xx 00 UNALLOCATED
10 00 SME2 lookup table expand four non-contiguous registers
10 01 UNALLOCATED
!= 00 1x UNALLOCATED
x1 0x SME2 lookup table expand two non-contiguous registers

SME2 lookup table two source registers expand to four non-contiguous destination registers

These instructions are under SME2 Expand Lookup Table (Non-contiguous).

313029282726252423222120191817161514131211109876543210
110000001001101100sizeopcZn0Zdh00Zdl
Decode fields Instruction Details Feature
opc
00 LUTI4 (four registers, 8-bit)FEAT_SME_LUTv2
01 UNALLOCATED-
1x UNALLOCATED-

SME2 lookup table expand four non-contiguous registers

These instructions are under SME2 Expand Lookup Table (Non-contiguous).

313029282726252423222120191817161514131211109876543210
1100000010011opc10sizeopc2ZnZdh00Zdl
Decode fields Instruction Details Feature
opc opc2
00x UNALLOCATED-
01x 00 LUTI4 (four registers, 16-bit & 32-bit)FEAT_SME2p1
01x 01 UNALLOCATED-
01x 1x UNALLOCATED-
1xx 00 LUTI2 (four registers)FEAT_SME2p1
1xx 01 UNALLOCATED-
1xx 1x UNALLOCATED-

SME2 lookup table expand two non-contiguous registers

These instructions are under SME2 Expand Lookup Table (Non-contiguous).

313029282726252423222120191817161514131211109876543210
1100000010011opc1sizeopc2ZnZdh0Zdl
Decode fields Instruction Details Feature
opc opc2
00xx UNALLOCATED-
01xx 00 LUTI4 (two registers)FEAT_SME2p1
01xx 01 UNALLOCATED-
01xx 1x UNALLOCATED-
1xxx 00 LUTI2 (two registers)FEAT_SME2p1
1xxx 01 UNALLOCATED-
1xxx 1x UNALLOCATED-

SME2 Multi-vector - Indexed (One register)

These instructions are under SME encodings.

313029282726252423222120191817161514131211109876543210
11000001op000op1op2
Decode fieldsInstruction detailsFeature
op0op1op2
00 SME2 multi-vec indexed long long MLA one source 32-bit-
01 000 FMLALL (multiple and indexed vector)One ZA quad-vectorFEAT_SME_F8F32
01 != 000 UNALLOCATED-
10 0 xx0 SME2 multi-vec indexed long long MLA one source 64-bit-
10 0 xx1 UNALLOCATED-
10 1 SME2 multi-vec indexed long FMA one source-
11 0 0xx FMLAL (multiple and indexed vector, FP8 to FP16)One ZA double-vectorFEAT_SME_F8F16
11 0 1xx UNALLOCATED-
11 1 SME2 multi-vec indexed long MLA one source-

SME2 multi-vec indexed long long MLA one source 32-bit

These instructions are under SME2 Multi-vector - Indexed (One register).

313029282726252423222120191817161514131211109876543210
110000010000Zmi4hRvi4lZnUSopoff2
Decode fields Instruction Details Feature
U S op
1 1 UNALLOCATED-
0 0 0 SMLALL (multiple and indexed vector)FEAT_SME2
0 0 1 USMLALL (multiple and indexed vector)FEAT_SME2
0 1 0 SMLSLL (multiple and indexed vector)FEAT_SME2
1 0 0 UMLALL (multiple and indexed vector)FEAT_SME2
1 0 1 SUMLALL (multiple and indexed vector)FEAT_SME2
1 1 0 UMLSLL (multiple and indexed vector)FEAT_SME2

SME2 multi-vec indexed long long MLA one source 64-bit

These instructions are under SME2 Multi-vector - Indexed (One register).

313029282726252423222120191817161514131211109876543210
110000011000Zmi3hRv0i3lZnUS0off2
Decode fields Instruction Details Feature
U S
0 0 SMLALL (multiple and indexed vector)FEAT_SME_I16I64
0 1 SMLSLL (multiple and indexed vector)FEAT_SME_I16I64
1 0 UMLALL (multiple and indexed vector)FEAT_SME_I16I64
1 1 UMLSLL (multiple and indexed vector)FEAT_SME_I16I64

SME2 multi-vec indexed long FMA one source

These instructions are under SME2 Multi-vector - Indexed (One register).

313029282726252423222120191817161514131211109876543210
110000011000Zmi3hRv1i3lZnopSoff3
Decode fields Instruction Details Feature
op S
0 0 FMLAL (multiple and indexed vector, FP16 to FP32)FEAT_SME2
0 1 FMLSL (multiple and indexed vector)FEAT_SME2
1 0 BFMLAL (multiple and indexed vector)FEAT_SME2
1 1 BFMLSL (multiple and indexed vector)FEAT_SME2

SME2 multi-vec indexed long MLA one source

These instructions are under SME2 Multi-vector - Indexed (One register).

313029282726252423222120191817161514131211109876543210
110000011100Zmi3hRv1i3lZnUSoff3
Decode fields Instruction Details Feature
U S
0 0 SMLAL (multiple and indexed vector)FEAT_SME2
0 1 SMLSL (multiple and indexed vector)FEAT_SME2
1 0 UMLAL (multiple and indexed vector)FEAT_SME2
1 1 UMLSL (multiple and indexed vector)FEAT_SME2

SME2 Multi-vector - Indexed (Two registers)

These instructions are under SME encodings.

313029282726252423222120191817161514131211109876543210
11000001op0010op1op2op3
Decode fieldsInstruction detailsFeature
op0op1op2op3
00 0x SME2 multi-vec indexed long long MLA two sources 32-bit-
00 1x SME2 multi-vec ternary indexed two registers 16-bit-
01 SME2 multi-vec ternary indexed two registers 32-bit-
10 00 0 SME2 multi-vec indexed long long MLA two sources 64-bit-
10 01 0 UNALLOCATED-
10 0x 1 00 FMLALL (multiple and indexed vector)Two ZA quad-vectorsFEAT_SME_F8F32
10 0x 1 != 00 UNALLOCATED-
10 1x 0 SME2 multi-vec indexed long FMA two sources-
10 1x 1 0x UNALLOCATED-
10 1x 1 1x FMLAL (multiple and indexed vector, FP8 to FP16)Two ZA double-vectorsFEAT_SME_F8F16
11 00 0 SME2 multi-vec ternary indexed two registers 64-bit-
11 01 0 SME2 multi-vec indexed FP8 two-way vertical dot product to single precision two registers-
11 1x 0 SME2 multi-vec indexed long MLA two sources-
11 1 0x SME2 multi-vec indexed FP8 two-way dot product to FP16 two registers-
11 1 1x UNALLOCATED-

SME2 multi-vec indexed long long MLA two sources 32-bit

These instructions are under SME2 Multi-vector - Indexed (Two registers).

313029282726252423222120191817161514131211109876543210
110000010001Zm0Rv0i4hZnopUSi4lo1
Decode fields Instruction Details Feature
op U S
0 0 0 SMLALL (multiple and indexed vector)FEAT_SME2
0 0 1 SMLSLL (multiple and indexed vector)FEAT_SME2
0 1 0 UMLALL (multiple and indexed vector)FEAT_SME2
0 1 1 UMLSLL (multiple and indexed vector)FEAT_SME2
1 1 UNALLOCATED-
1 0 0 USMLALL (multiple and indexed vector)FEAT_SME2
1 1 0 SUMLALL (multiple and indexed vector)FEAT_SME2

SME2 multi-vec ternary indexed two registers 16-bit

These instructions are under SME2 Multi-vector - Indexed (Two registers).

313029282726252423222120191817161514131211109876543210
110000010001Zm0Rv1i3hZnopSi3loff3
Decode fields Instruction Details Feature
op S
0 0 FMLA (multiple and indexed vector)FEAT_SME_F16F16
0 1 FMLS (multiple and indexed vector)FEAT_SME_F16F16
1 0 BFMLA (multiple and indexed vector)FEAT_SVE_B16B16
1 1 BFMLS (multiple and indexed vector)FEAT_SVE_B16B16

SME2 multi-vec ternary indexed two registers 32-bit

These instructions are under SME2 Multi-vector - Indexed (Two registers).

313029282726252423222120191817161514131211109876543210
110000010101Zm0Rvopi2Znopc2off3
Decode fields Instruction Details Feature
op opc2
0 000 FMLA (multiple and indexed vector)FEAT_SME2
0 001 FVDOT (FP16 to FP32)FEAT_SME2
0 010 FMLS (multiple and indexed vector)FEAT_SME2
0 011 BFVDOTFEAT_SME2
0 100 SVDOT (2-way)FEAT_SME2
0 101 UNALLOCATED-
0 110 UVDOT (2-way)FEAT_SME2
0 111 FDOT (4-way, multiple and indexed vector)FEAT_SME_F8F32
1 000 SDOT (2-way, multiple and indexed vector)FEAT_SME2
1 001 FDOT (2-way, multiple and indexed vector, FP16 to FP32)FEAT_SME2
1 010 UDOT (2-way, multiple and indexed vector)FEAT_SME2
1 011 BFDOT (multiple and indexed vector)FEAT_SME2
1 100 SDOT (4-way, multiple and indexed vector)FEAT_SME2
1 101 USDOT (multiple and indexed vector)FEAT_SME2
1 110 UDOT (4-way, multiple and indexed vector)FEAT_SME2
1 111 SUDOT (multiple and indexed vector)FEAT_SME2

SME2 multi-vec indexed long long MLA two sources 64-bit

These instructions are under SME2 Multi-vector - Indexed (Two registers).

313029282726252423222120191817161514131211109876543210
110000011001Zm0Rv00i3hZn0USi3lo1
Decode fields Instruction Details Feature
U S
0 0 SMLALL (multiple and indexed vector)FEAT_SME_I16I64
0 1 SMLSLL (multiple and indexed vector)FEAT_SME_I16I64
1 0 UMLALL (multiple and indexed vector)FEAT_SME_I16I64
1 1 UMLSLL (multiple and indexed vector)FEAT_SME_I16I64

SME2 multi-vec indexed long FMA two sources

These instructions are under SME2 Multi-vector - Indexed (Two registers).

313029282726252423222120191817161514131211109876543210
110000011001Zm0Rv1i3hZn0opSi3loff2
Decode fields Instruction Details Feature
op S
0 0 FMLAL (multiple and indexed vector, FP16 to FP32)FEAT_SME2
0 1 FMLSL (multiple and indexed vector)FEAT_SME2
1 0 BFMLAL (multiple and indexed vector)FEAT_SME2
1 1 BFMLSL (multiple and indexed vector)FEAT_SME2

SME2 multi-vec ternary indexed two registers 64-bit

These instructions are under SME2 Multi-vector - Indexed (Two registers).

313029282726252423222120191817161514131211109876543210
110000011101Zm0Rv00i1Zn0opcoff3
Decode fields Instruction Details Feature
opc
00 FMLA (multiple and indexed vector)FEAT_SME_F64F64
01 SDOT (4-way, multiple and indexed vector)FEAT_SME_I16I64
10 FMLS (multiple and indexed vector)FEAT_SME_F64F64
11 UDOT (4-way, multiple and indexed vector)FEAT_SME_I16I64

SME2 multi-vec indexed FP8 two-way vertical dot product to single precision two registers

These instructions are under SME2 Multi-vector - Indexed (Two registers).

313029282726252423222120191817161514131211109876543210
110000011101Zm0Rv01i2hZn0Ti2loff3
Decode fields Instruction Details Feature
T
0 FVDOTBFEAT_SME_F8F32
1 FVDOTTFEAT_SME_F8F32

SME2 multi-vec indexed long MLA two sources

These instructions are under SME2 Multi-vector - Indexed (Two registers).

313029282726252423222120191817161514131211109876543210
110000011101Zm0Rv1i3hZn0USi3loff2
Decode fields Instruction Details Feature
U S
0 0 SMLAL (multiple and indexed vector)FEAT_SME2
0 1 SMLSL (multiple and indexed vector)FEAT_SME2
1 0 UMLAL (multiple and indexed vector)FEAT_SME2
1 1 UMLSL (multiple and indexed vector)FEAT_SME2

SME2 multi-vec indexed FP8 two-way dot product to FP16 two registers

These instructions are under SME2 Multi-vector - Indexed (Two registers).

313029282726252423222120191817161514131211109876543210
110000011101Zm0Rvopi3hZn10i3loff3
Decode fields Instruction Details Feature
op
0 FDOT (2-way, multiple and indexed vector, FP8 to FP16)FEAT_SME_F8F16
1 FVDOT (FP8 to FP16)FEAT_SME_F8F16

SME2 Multi-vector - Indexed (Four registers)

These instructions are under SME encodings.

313029282726252423222120191817161514131211109876543210
11000001op0011op1op2op3
Decode fieldsInstruction detailsFeature
op0op1op2op3
00 0x 0xx SME2 multi-vec indexed long long MLA four sources 32-bit-
00 0x 100 0 FMLALL (multiple and indexed vector)Four ZA quad-vectorsFEAT_SME_F8F32
00 0x 100 1 UNALLOCATED-
00 1x 0xx SME2 multi-vec ternary indexed four registers 16-bit-
00 1x 100 FDOT (2-way, multiple and indexed vector, FP8 to FP16)Four ZA single-vectorsFEAT_SME_F8F16
00 1!= 00 UNALLOCATED-
01 0xx SME2 multi-vec ternary indexed four registers 32-bit-
10 00 00x SME2 multi-vec indexed long long MLA four sources 64-bit-
10 00 != 00x UNALLOCATED-
10 01 UNALLOCATED-
10 1x 00x SME2 multi-vec indexed long FMA four sources-
10 1x 010 FMLAL (multiple and indexed vector, FP8 to FP16)Four ZA double-vectorsFEAT_SME_F8F16
10 1x 011 UNALLOCATED-
10 1x 1xx UNALLOCATED-
11 0x 00x SME2 multi-vec ternary indexed four registers 64-bit-
11 1x 00x SME2 multi-vec indexed long MLA four sources-
11 01x UNALLOCATED-
x1 1xx UNALLOCATED-

SME2 multi-vec indexed long long MLA four sources 32-bit

These instructions are under SME2 Multi-vector - Indexed (Four registers).

313029282726252423222120191817161514131211109876543210
110000010001Zm1Rv0i4hZn0opUSi4lo1
Decode fields Instruction Details Feature
op U S
0 0 0 SMLALL (multiple and indexed vector)FEAT_SME2
0 0 1 SMLSLL (multiple and indexed vector)FEAT_SME2
0 1 0 UMLALL (multiple and indexed vector)FEAT_SME2
0 1 1 UMLSLL (multiple and indexed vector)FEAT_SME2
1 1 UNALLOCATED-
1 0 0 USMLALL (multiple and indexed vector)FEAT_SME2
1 1 0 SUMLALL (multiple and indexed vector)FEAT_SME2

SME2 multi-vec ternary indexed four registers 16-bit

These instructions are under SME2 Multi-vector - Indexed (Four registers).

313029282726252423222120191817161514131211109876543210
110000010001Zm1Rv1i3hZn0opSi3loff3
Decode fields Instruction Details Feature
op S
0 0 FMLA (multiple and indexed vector)FEAT_SME_F16F16
0 1 FMLS (multiple and indexed vector)FEAT_SME_F16F16
1 0 BFMLA (multiple and indexed vector)FEAT_SVE_B16B16
1 1 BFMLS (multiple and indexed vector)FEAT_SVE_B16B16

SME2 multi-vec ternary indexed four registers 32-bit

These instructions are under SME2 Multi-vector - Indexed (Four registers).

313029282726252423222120191817161514131211109876543210
110000010101Zm1Rvopi2Zn0opc2off3
Decode fields Instruction Details Feature
op opc2
0 000 FMLA (multiple and indexed vector)FEAT_SME2
0 001 FDOT (4-way, multiple and indexed vector)FEAT_SME_F8F32
0 010 FMLS (multiple and indexed vector)FEAT_SME2
0 011 UNALLOCATED-
0 100 SVDOT (4-way)FEAT_SME2
0 101 USVDOTFEAT_SME2
0 110 UVDOT (4-way)FEAT_SME2
0 111 SUVDOTFEAT_SME2
1 000 SDOT (2-way, multiple and indexed vector)FEAT_SME2
1 001 FDOT (2-way, multiple and indexed vector, FP16 to FP32)FEAT_SME2
1 010 UDOT (2-way, multiple and indexed vector)FEAT_SME2
1 011 BFDOT (multiple and indexed vector)FEAT_SME2
1 100 SDOT (4-way, multiple and indexed vector)FEAT_SME2
1 101 USDOT (multiple and indexed vector)FEAT_SME2
1 110 UDOT (4-way, multiple and indexed vector)FEAT_SME2
1 111 SUDOT (multiple and indexed vector)FEAT_SME2

SME2 multi-vec indexed long long MLA four sources 64-bit

These instructions are under SME2 Multi-vector - Indexed (Four registers).

313029282726252423222120191817161514131211109876543210
110000011001Zm1Rv00i3hZn00USi3lo1
Decode fields Instruction Details Feature
U S
0 0 SMLALL (multiple and indexed vector)FEAT_SME_I16I64
0 1 SMLSLL (multiple and indexed vector)FEAT_SME_I16I64
1 0 UMLALL (multiple and indexed vector)FEAT_SME_I16I64
1 1 UMLSLL (multiple and indexed vector)FEAT_SME_I16I64

SME2 multi-vec indexed long FMA four sources

These instructions are under SME2 Multi-vector - Indexed (Four registers).

313029282726252423222120191817161514131211109876543210
110000011001Zm1Rv1i3hZn00opSi3loff2
Decode fields Instruction Details Feature
op S
0 0 FMLAL (multiple and indexed vector, FP16 to FP32)FEAT_SME2
0 1 FMLSL (multiple and indexed vector)FEAT_SME2
1 0 BFMLAL (multiple and indexed vector)FEAT_SME2
1 1 BFMLSL (multiple and indexed vector)FEAT_SME2

SME2 multi-vec ternary indexed four registers 64-bit

These instructions are under SME2 Multi-vector - Indexed (Four registers).

313029282726252423222120191817161514131211109876543210
110000011101Zm1Rv0opi1Zn00opc2off3
Decode fields Instruction Details Feature
op opc2
0 00 FMLA (multiple and indexed vector)FEAT_SME_F64F64
0 01 SDOT (4-way, multiple and indexed vector)FEAT_SME_I16I64
0 10 FMLS (multiple and indexed vector)FEAT_SME_F64F64
0 11 UDOT (4-way, multiple and indexed vector)FEAT_SME_I16I64
1 x0 UNALLOCATED-
1 01 SVDOT (4-way)FEAT_SME_I16I64
1 11 UVDOT (4-way)FEAT_SME_I16I64

SME2 multi-vec indexed long MLA four sources

These instructions are under SME2 Multi-vector - Indexed (Four registers).

313029282726252423222120191817161514131211109876543210
110000011101Zm1Rv1i3hZn00USi3loff2
Decode fields Instruction Details Feature
U S
0 0 SMLAL (multiple and indexed vector)FEAT_SME2
0 1 SMLSL (multiple and indexed vector)FEAT_SME2
1 0 UMLAL (multiple and indexed vector)FEAT_SME2
1 1 UMLSL (multiple and indexed vector)FEAT_SME2

SME2 Multi-vector - SVE Select

These instructions are under SME encodings.

313029282726252423222120191817161514131211109876543210
110000011op0100op1op2
Decode fieldsInstruction detailsFeature
op0op1op2
01 00 00 SELFour registersFEAT_SME2
01 00 != 00 UNALLOCATED-
01 != 00 UNALLOCATED-
11 UNALLOCATED-
x0 x0 x0 SELTwo registersFEAT_SME2
x0 x0 x1 UNALLOCATED-
x0 x1 UNALLOCATED-

SME2 Multi-vector - SVE Constructive Binary

These instructions are under SME encodings.

313029282726252423222120191817161514131211109876543210
11000001op01110op1op2
Decode fieldsInstruction details
op0op1op2
00 101 SME2 multi-vec quadwords ZIP two registers
01 101 UNALLOCATED
10 101 UNALLOCATED
11 101 SME2 multi-vec saturating shift right narrow two registers
000 SME2 multi-vec FCLAMP two registers
001 SME2 multi-vec CLAMP two registers
010 0 SME2 multi-vec FCLAMP four registers
011 0 SME2 multi-vec CLAMP four registers
01x 1 UNALLOCATED
100 SME2 multi-vec ZIP two registers
11x SME2 multi-vec saturating shift right narrow four registers

SME2 multi-vec quadwords ZIP two registers

These instructions are under SME2 Multi-vector - SVE Constructive Binary.

313029282726252423222120191817161514131211109876543210
11000001001Zm110101ZnZdop
Decode fields Instruction Details Feature
op
0 ZIP (two registers)FEAT_SME2
1 UZP (two registers)FEAT_SME2

SME2 multi-vec saturating shift right narrow two registers

These instructions are under SME2 Multi-vector - SVE Constructive Binary.

313029282726252423222120191817161514131211109876543210
11000001111opimm4110101ZnUZd
Decode fields Instruction Details Feature
op U
0 0 SQRSHR (two registers)FEAT_SME2
0 1 UQRSHR (two registers)FEAT_SME2
1 0 SQRSHRU (two registers)FEAT_SME2
1 1 UNALLOCATED-

SME2 multi-vec FCLAMP two registers

These instructions are under SME2 Multi-vector - SVE Constructive Binary.

313029282726252423222120191817161514131211109876543210
11000001size1Zm110000ZnZdop
Decode fields Instruction Details Feature
size op
1 UNALLOCATED-
!= 00 0 FCLAMPFEAT_SME2
00 0 BFCLAMPFEAT_SVE_B16B16

SME2 multi-vec CLAMP two registers

These instructions are under SME2 Multi-vector - SVE Constructive Binary.

313029282726252423222120191817161514131211109876543210
11000001size1Zm110001ZnZdU
Decode fields Instruction Details Feature
U
0 SCLAMPFEAT_SME2
1 UCLAMPFEAT_SME2

SME2 multi-vec FCLAMP four registers

These instructions are under SME2 Multi-vector - SVE Constructive Binary.

313029282726252423222120191817161514131211109876543210
11000001size1Zm110010ZnZd0op
Decode fields Instruction Details Feature
size op
1 UNALLOCATED-
!= 00 0 FCLAMPFEAT_SME2
00 0 BFCLAMPFEAT_SVE_B16B16

SME2 multi-vec CLAMP four registers

These instructions are under SME2 Multi-vector - SVE Constructive Binary.

313029282726252423222120191817161514131211109876543210
11000001size1Zm110011ZnZd0U
Decode fields Instruction Details Feature
U
0 SCLAMPFEAT_SME2
1 UCLAMPFEAT_SME2

SME2 multi-vec ZIP two registers

These instructions are under SME2 Multi-vector - SVE Constructive Binary.

313029282726252423222120191817161514131211109876543210
11000001size1Zm110100ZnZdop
Decode fields Instruction Details Feature
op
0 ZIP (two registers)FEAT_SME2
1 UZP (two registers)FEAT_SME2

SME2 multi-vec saturating shift right narrow four registers

These instructions are under SME2 Multi-vector - SVE Constructive Binary.

313029282726252423222120191817161514131211109876543210
11000001tsize1imm511011NZnopUZd
Decode fields Instruction Details Feature
N op U
1 1 UNALLOCATED-
0 0 0 SQRSHR (four registers)FEAT_SME2
0 0 1 UQRSHR (four registers)FEAT_SME2
0 1 0 SQRSHRU (four registers)FEAT_SME2
1 0 0 SQRSHRNFEAT_SME2
1 0 1 UQRSHRNFEAT_SME2
1 1 0 SQRSHRUNFEAT_SME2

SME2 Multi-vector - SVE Constructive Unary

These instructions are under SME encodings.

313029282726252423222120191817161514131211109876543210
11000001op01op1op2111000op3op4
Decode fieldsInstruction details
op0op1op2op3op4
00 000 01 x0 SME2 multi-vec FP to int convert two registers
00 000 01 x1 UNALLOCATED
00 000 10 x0 SME2 multi-vec int to FP two registers
00 000 10 x1 UNALLOCATED
00 001 11 UNALLOCATED
00 100 00 UNALLOCATED
00 100 01 0x 00 SME2 multi-vec FP to int convert four registers
00 100 01 0x != 00 UNALLOCATED
00 100 01 1x UNALLOCATED
00 100 10 0x 00 SME2 multi-vec int to FP four registers
00 100 10 0x != 00 UNALLOCATED
00 100 10 1x UNALLOCATED
00 101 00 0x SME2 multi-vec FP8 down convert four registers
00 101 00 1x UNALLOCATED
00 101 11 00 x0 SME2 multi-vec quadwords ZIP four registers
00 101 1x 00 x1 UNALLOCATED
00 101 1x != 00 UNALLOCATED
01 000 01 UNALLOCATED
01 101 00 UNALLOCATED
01 x00 10 UNALLOCATED
0x 000 00 SME2 multi-vec FP down convert two registers
0x 000 11 SME2 multi-vec int down convert two registers
0x 001 00 x0 SME2 multi-vec FP8 down convert two registers
0x 001 00 x1 UNALLOCATED
10 000 00 SME2 multi-vec convert two registers
10 000 != 00 UNALLOCATED
11 000 UNALLOCATED
1x 100 10 UNALLOCATED
1x x01 00 UNALLOCATED
!= 00 100 0x UNALLOCATED
!= 00 101 10 00 x1 UNALLOCATED
!= 00 101 10 01 UNALLOCATED
!= 00 101 10 1x UNALLOCATED
!= 00 x01 11 UNALLOCATED
001 01 SME2 multi-vec unpack two registers
001 10 SME2 multi-vec FP8 up convert two registers
01x x0 x0 SME2 multi-vec FRINT two registers
01x x0 x1 UNALLOCATED
01x x1 UNALLOCATED
100 11 SME2 multi-vec int down convert four registers
101 01 x0 0x SME2 multi-vec unpack four registers
101 01 x0 1x UNALLOCATED
101 01 x1 UNALLOCATED
101 10 00 x0 SME2 multi-vec ZIP four registers
11x 00 00 SME2 multi-vec FRINT four registers
11x 00 != 00 UNALLOCATED
11x != 00 UNALLOCATED

SME2 multi-vec FP to int convert two registers

These instructions are under SME2 Multi-vector - SVE Constructive Unary.

313029282726252423222120191817161514131211109876543210
1100000100100001111000ZnUZd0
Decode fields Instruction Details Feature
U
0 FCVTZSFEAT_SME2
1 FCVTZUFEAT_SME2

SME2 multi-vec int to FP two registers

These instructions are under SME2 Multi-vector - SVE Constructive Unary.

313029282726252423222120191817161514131211109876543210
1100000100100010111000ZnUZd0
Decode fields Instruction Details Feature
U
0 SCVTFFEAT_SME2
1 UCVTFFEAT_SME2

SME2 multi-vec FP to int convert four registers

These instructions are under SME2 Multi-vector - SVE Constructive Unary.

313029282726252423222120191817161514131211109876543210
1100000100110001111000Zn0UZd00
Decode fields Instruction Details Feature
U
0 FCVTZSFEAT_SME2
1 FCVTZUFEAT_SME2

SME2 multi-vec int to FP four registers

These instructions are under SME2 Multi-vector - SVE Constructive Unary.

313029282726252423222120191817161514131211109876543210
1100000100110010111000Zn0UZd00
Decode fields Instruction Details Feature
U
0 SCVTFFEAT_SME2
1 UCVTFFEAT_SME2

SME2 multi-vec FP8 down convert four registers

These instructions are under SME2 Multi-vector - SVE Constructive Unary.

313029282726252423222120191817161514131211109876543210
1100000100110100111000Zn0NZd
Decode fields Instruction Details Feature
N
0 FCVT (narrowing, FP32 to FP8)FEAT_FP8
1 FCVTN (FP32 to FP8)FEAT_FP8

SME2 multi-vec quadwords ZIP four registers

These instructions are under SME2 Multi-vector - SVE Constructive Unary.

313029282726252423222120191817161514131211109876543210
1100000100110111111000Zn00Zdop0
Decode fields Instruction Details Feature
op
0 ZIP (four registers)FEAT_SME2
1 UZP (four registers)FEAT_SME2

SME2 multi-vec FP down convert two registers

These instructions are under SME2 Multi-vector - SVE Constructive Unary.

313029282726252423222120191817161514131211109876543210
110000010op100000111000ZnNZd
Decode fields Instruction Details Feature
op N
0 0 FCVT (narrowing, FP32 to FP16)FEAT_SME2
0 1 FCVTN (FP32 to FP16)FEAT_SME2
1 0 BFCVTFEAT_SME2
1 1 BFCVTNFEAT_SME2

SME2 multi-vec int down convert two registers

These instructions are under SME2 Multi-vector - SVE Constructive Unary.

313029282726252423222120191817161514131211109876543210
110000010op100011111000ZnUZd
Decode fields Instruction Details Feature
op U
0 0 SQCVT (two registers)FEAT_SME2
0 1 UQCVT (two registers)FEAT_SME2
1 0 SQCVTU (two registers)FEAT_SME2
1 1 UNALLOCATED-

SME2 multi-vec FP8 down convert two registers

These instructions are under SME2 Multi-vector - SVE Constructive Unary.

313029282726252423222120191817161514131211109876543210
110000010op100100111000Zn0Zd
Decode fields Instruction Details Feature
op
0 FCVT (narrowing, FP16 to FP8)FEAT_FP8
1 BFCVTFEAT_FP8

SME2 multi-vec convert two registers

These instructions are under SME2 Multi-vector - SVE Constructive Unary.

313029282726252423222120191817161514131211109876543210
1100000110100000111000ZnZdL
Decode fields Instruction Details Feature
L
0 FCVT (widening)FEAT_SME_F16F16
1 FCVTLFEAT_SME_F16F16

SME2 multi-vec unpack two registers

These instructions are under SME2 Multi-vector - SVE Constructive Unary.

313029282726252423222120191817161514131211109876543210
11000001size100101111000ZnZdU
Decode fields Instruction Details Feature
U
0 SUNPKFEAT_SME2
1 UUNPKFEAT_SME2

SME2 multi-vec FP8 up convert two registers

These instructions are under SME2 Multi-vector - SVE Constructive Unary.

313029282726252423222120191817161514131211109876543210
11000001opc100110111000ZnZdL
Decode fields Instruction Details Feature
opc L
00 0 F1CVT, F2CVTF1CVTFEAT_FP8
00 1 F1CVTL, F2CVTLF1CVTLFEAT_FP8
01 0 BF1CVT, BF2CVTBF1CVTFEAT_FP8
01 1 BF1CVTL, BF2CVTLBF1CVTLFEAT_FP8
10 0 F1CVT, F2CVTF2CVTFEAT_FP8
10 1 F1CVTL, F2CVTLF2CVTLFEAT_FP8
11 0 BF1CVT, BF2CVTBF2CVTFEAT_FP8
11 1 BF1CVTL, BF2CVTLBF2CVTLFEAT_FP8

SME2 multi-vec FRINT two registers

These instructions are under SME2 Multi-vector - SVE Constructive Unary.

313029282726252423222120191817161514131211109876543210
11000001size101opc111000Zn0Zd0
Decode fields Instruction Details Feature
size opc
0x UNALLOCATED-
10 000 FRINTNFEAT_SME2
10 001 FRINTPFEAT_SME2
10 010 FRINTMFEAT_SME2
10 011 UNALLOCATED-
10 100 FRINTAFEAT_SME2
10 101 UNALLOCATED-
10 11x UNALLOCATED-
11 UNALLOCATED-

SME2 multi-vec int down convert four registers

These instructions are under SME2 Multi-vector - SVE Constructive Unary.

313029282726252423222120191817161514131211109876543210
11000001szop110011111000ZnNUZd
Decode fields Instruction Details Feature
op N U
0 0 0 SQCVT (four registers)FEAT_SME2
0 0 1 UQCVT (four registers)FEAT_SME2
0 1 0 SQCVTNFEAT_SME2
0 1 1 UQCVTNFEAT_SME2
1 1 UNALLOCATED-
1 0 0 SQCVTU (four registers)FEAT_SME2
1 1 0 SQCVTUNFEAT_SME2

SME2 multi-vec unpack four registers

These instructions are under SME2 Multi-vector - SVE Constructive Unary.

313029282726252423222120191817161514131211109876543210
11000001size110101111000Zn0Zd0U
Decode fields Instruction Details Feature
U
0 SUNPKFEAT_SME2
1 UUNPKFEAT_SME2

SME2 multi-vec ZIP four registers

These instructions are under SME2 Multi-vector - SVE Constructive Unary.

313029282726252423222120191817161514131211109876543210
11000001size110110111000Zn00Zdop0
Decode fields Instruction Details Feature
op
0 ZIP (four registers)FEAT_SME2
1 UZP (four registers)FEAT_SME2

SME2 multi-vec FRINT four registers

These instructions are under SME2 Multi-vector - SVE Constructive Unary.

313029282726252423222120191817161514131211109876543210
11000001size111opc111000Zn00Zd00
Decode fields Instruction Details Feature
size opc
0x UNALLOCATED-
10 000 FRINTNFEAT_SME2
10 001 FRINTPFEAT_SME2
10 010 FRINTMFEAT_SME2
10 011 UNALLOCATED-
10 100 FRINTAFEAT_SME2
10 101 UNALLOCATED-
10 11x UNALLOCATED-
11 UNALLOCATED-

SME2 Multi-vector - Multiple Vectors SVE Destructive (Two registers)

These instructions are under SME encodings.

313029282726252423222120191817161514131211109876543210
1100000110101100op0
Decode fieldsInstruction details
op0
000 SME2 multiple vectors int min/max two registers
001 UNALLOCATED
010 SME2 multiple vectors FP min/max two registers
011 SME2 multiple vectors FSCALE two registers
10x SME2 multiple vectors shift two registers
11x UNALLOCATED

SME2 multiple vectors int min/max two registers

These instructions are under SME2 Multi-vector - Multiple Vectors SVE Destructive (Two registers).

313029282726252423222120191817161514131211109876543210
11000001size1Zm0101100000opcZdnU
Decode fields Instruction Details Feature
opc U
00 0 SMAX (multiple vectors)FEAT_SME2
00 1 UMAX (multiple vectors)FEAT_SME2
01 0 SMIN (multiple vectors)FEAT_SME2
01 1 UMIN (multiple vectors)FEAT_SME2
1x UNALLOCATED-

SME2 multiple vectors FP min/max two registers

These instructions are under SME2 Multi-vector - Multiple Vectors SVE Destructive (Two registers).

313029282726252423222120191817161514131211109876543210
11000001size1Zm0101100010opcZdno2
Decode fields Instruction Details Feature
size opc o2
10 0 FAMAXFEAT_FAMINMAX
10 1 FAMINFEAT_FAMINMAX
11 UNALLOCATED-
!= 00 00 0 FMAX (multiple vectors)FEAT_SME2
!= 00 00 1 FMIN (multiple vectors)FEAT_SME2
!= 00 01 0 FMAXNM (multiple vectors)FEAT_SME2
!= 00 01 1 FMINNM (multiple vectors)FEAT_SME2
00 00 0 BFMAX (multiple vectors)FEAT_SVE_B16B16
00 00 1 BFMIN (multiple vectors)FEAT_SVE_B16B16
00 01 0 BFMAXNM (multiple vectors)FEAT_SVE_B16B16
00 01 1 BFMINNM (multiple vectors)FEAT_SVE_B16B16

SME2 multiple vectors FSCALE two registers

These instructions are under SME2 Multi-vector - Multiple Vectors SVE Destructive (Two registers).

313029282726252423222120191817161514131211109876543210
11000001size1Zm0101100011opcZdno2
Decode fields Instruction Details Feature
opc o2
00 0 FSCALE (multiple vectors)FEAT_FP8
00 1 UNALLOCATED-
01 UNALLOCATED-
1x UNALLOCATED-

SME2 multiple vectors shift two registers

These instructions are under SME2 Multi-vector - Multiple Vectors SVE Destructive (Two registers).

313029282726252423222120191817161514131211109876543210
11000001size1Zm010110010opcZdnU
Decode fields Instruction Details Feature
opc U
000 UNALLOCATED-
001 0 SRSHL (multiple vectors)FEAT_SME2
001 1 URSHL (multiple vectors)FEAT_SME2
01x UNALLOCATED-
1xx UNALLOCATED-

SME2 Multi-vector - Multiple Vectors SVE Saturating Multiply (Two registers)

These instructions are under SME encodings.

313029282726252423222120191817161514131211109876543210
1100000110101101op0
Decode fieldsInstruction details
op0
00000 SME2 multi-vector signed saturating doubling multiply high two registers
!= 00000 UNALLOCATED

SME2 multi-vector signed saturating doubling multiply high two registers

These instructions are under SME2 Multi-vector - Multiple Vectors SVE Saturating Multiply (Two registers).

313029282726252423222120191817161514131211109876543210
11000001size1Zm010110100000Zdnop
Decode fields Instruction Details Feature
op
0 SQDMULH (multiple vectors)FEAT_SME2
1 UNALLOCATED-

SME2 Multi-vector - Multiple Vectors SVE Destructive (Four registers)

These instructions are under SME encodings.

313029282726252423222120191817161514131211109876543210
11000001100101110op00
Decode fieldsInstruction details
op0
000 SME2 multiple vectors int min/max four registers
001 UNALLOCATED
010 SME2 multiple vectors FP min/max four registers
011 SME2 multiple vectors FSCALE four registers
10x SME2 multiple vectors shift four registers
11x UNALLOCATED

SME2 multiple vectors int min/max four registers

These instructions are under SME2 Multi-vector - Multiple Vectors SVE Destructive (Four registers).

313029282726252423222120191817161514131211109876543210
11000001size1Zm00101110000opcZdn0U
Decode fields Instruction Details Feature
opc U
00 0 SMAX (multiple vectors)FEAT_SME2
00 1 UMAX (multiple vectors)FEAT_SME2
01 0 SMIN (multiple vectors)FEAT_SME2
01 1 UMIN (multiple vectors)FEAT_SME2
1x UNALLOCATED-

SME2 multiple vectors FP min/max four registers

These instructions are under SME2 Multi-vector - Multiple Vectors SVE Destructive (Four registers).

313029282726252423222120191817161514131211109876543210
11000001size1Zm00101110010opcZdn0o2
Decode fields Instruction Details Feature
size opc o2
10 0 FAMAXFEAT_FAMINMAX
10 1 FAMINFEAT_FAMINMAX
11 UNALLOCATED-
!= 00 00 0 FMAX (multiple vectors)FEAT_SME2
!= 00 00 1 FMIN (multiple vectors)FEAT_SME2
!= 00 01 0 FMAXNM (multiple vectors)FEAT_SME2
!= 00 01 1 FMINNM (multiple vectors)FEAT_SME2
00 00 0 BFMAX (multiple vectors)FEAT_SVE_B16B16
00 00 1 BFMIN (multiple vectors)FEAT_SVE_B16B16
00 01 0 BFMAXNM (multiple vectors)FEAT_SVE_B16B16
00 01 1 BFMINNM (multiple vectors)FEAT_SVE_B16B16

SME2 multiple vectors FSCALE four registers

These instructions are under SME2 Multi-vector - Multiple Vectors SVE Destructive (Four registers).

313029282726252423222120191817161514131211109876543210
11000001size1Zm00101110011opcZdn0o2
Decode fields Instruction Details Feature
opc o2
00 0 FSCALE (multiple vectors)FEAT_FP8
00 1 UNALLOCATED-
01 UNALLOCATED-
1x UNALLOCATED-

SME2 multiple vectors shift four registers

These instructions are under SME2 Multi-vector - Multiple Vectors SVE Destructive (Four registers).

313029282726252423222120191817161514131211109876543210
11000001size1Zm0010111010opcZdn0U
Decode fields Instruction Details Feature
opc U
000 UNALLOCATED-
001 0 SRSHL (multiple vectors)FEAT_SME2
001 1 URSHL (multiple vectors)FEAT_SME2
01x UNALLOCATED-
1xx UNALLOCATED-

SME2 Multi-vector - Multiple Vectors SVE Saturating Multiply (Four registers)

These instructions are under SME encodings.

313029282726252423222120191817161514131211109876543210
11000001100101111op00
Decode fieldsInstruction details
op0
00000 SME2 multi-vector signed saturating doubling multiply high four registers
!= 00000 UNALLOCATED

SME2 multi-vector signed saturating doubling multiply high four registers

These instructions are under SME2 Multi-vector - Multiple Vectors SVE Saturating Multiply (Four registers).

313029282726252423222120191817161514131211109876543210
11000001size1Zm0010111100000Zdn0op
Decode fields Instruction Details Feature
op
0 SQDMULH (multiple vectors)FEAT_SME2
1 UNALLOCATED-

SME2 Multi-vector - Multiple and Single SVE Destructive (Two registers)

These instructions are under SME encodings.

313029282726252423222120191817161514131211109876543210
110000011010100op0op1op2
Decode fieldsInstruction details
op0op1op2
0 00 00x SME2 single-multi int min/max two registers
0 01 00x SME2 single-multi FP min/max two registers
0 01 100 SME2 multiple and single vector FSCALE two registers
0 01 101 UNALLOCATED
0 01 x1x UNALLOCATED
0 10 SME2 single-multi shift two registers
0 11 000 SME2 single-multi add two registers
0 11 != 000 UNALLOCATED
1 00 000 SME2 single-multi signed saturating doubling multiply high two registers
1 00 001 UNALLOCATED
1 != 00 UNALLOCATED
00 != 00x UNALLOCATED

SME2 single-multi int min/max two registers

These instructions are under SME2 Multi-vector - Multiple and Single SVE Destructive (Two registers).

313029282726252423222120191817161514131211109876543210
11000001size10Zm1010000000opZdnU
Decode fields Instruction Details Feature
op U
0 0 SMAX (multiple and single vector)FEAT_SME2
0 1 UMAX (multiple and single vector)FEAT_SME2
1 0 SMIN (multiple and single vector)FEAT_SME2
1 1 UMIN (multiple and single vector)FEAT_SME2

SME2 single-multi FP min/max two registers

These instructions are under SME2 Multi-vector - Multiple and Single SVE Destructive (Two registers).

313029282726252423222120191817161514131211109876543210
11000001size10Zm1010000100opZdno2
Decode fields Instruction Details Feature
size op o2
!= 00 0 0 FMAX (multiple and single vector)FEAT_SME2
!= 00 0 1 FMIN (multiple and single vector)FEAT_SME2
!= 00 1 0 FMAXNM (multiple and single vector)FEAT_SME2
!= 00 1 1 FMINNM (multiple and single vector)FEAT_SME2
00 0 0 BFMAX (multiple and single vector)FEAT_SVE_B16B16
00 0 1 BFMIN (multiple and single vector)FEAT_SVE_B16B16
00 1 0 BFMAXNM (multiple and single vector)FEAT_SVE_B16B16
00 1 1 BFMINNM (multiple and single vector)FEAT_SVE_B16B16

SME2 multiple and single vector FSCALE two registers

These instructions are under SME2 Multi-vector - Multiple and Single SVE Destructive (Two registers).

313029282726252423222120191817161514131211109876543210
11000001size10Zm10100001100Zdnop
Decode fields Instruction Details Feature
op
0 FSCALE (multiple and single vector)FEAT_FP8
1 UNALLOCATED-

SME2 single-multi shift two registers

These instructions are under SME2 Multi-vector - Multiple and Single SVE Destructive (Two registers).

313029282726252423222120191817161514131211109876543210
11000001size10Zm10100010opcZdnU
Decode fields Instruction Details Feature
opc U
000 UNALLOCATED-
001 0 SRSHL (multiple and single vector)FEAT_SME2
001 1 URSHL (multiple and single vector)FEAT_SME2
01x UNALLOCATED-
1xx UNALLOCATED-

SME2 single-multi add two registers

These instructions are under SME2 Multi-vector - Multiple and Single SVE Destructive (Two registers).

313029282726252423222120191817161514131211109876543210
11000001size10Zm10100011000Zdnop
Decode fields Instruction Details Feature
op
0 ADD (to vector)FEAT_SME2
1 UNALLOCATED-

SME2 single-multi signed saturating doubling multiply high two registers

These instructions are under SME2 Multi-vector - Multiple and Single SVE Destructive (Two registers).

313029282726252423222120191817161514131211109876543210
11000001size10Zm10100100000Zdnop
Decode fields Instruction Details Feature
op
0 SQDMULH (multiple and single vector)FEAT_SME2
1 UNALLOCATED-

SME2 Multi-vector - Multiple and Single SVE Destructive (Four registers)

These instructions are under SME encodings.

313029282726252423222120191817161514131211109876543210
110000011010101op0op1op20
Decode fieldsInstruction details
op0op1op2
0 00 00x SME2 single-multi int min/max four registers
0 01 00x SME2 single-multi FP min/max four registers
0 01 100 SME2 multiple and single vector FSCALE four registers
0 01 101 UNALLOCATED
0 01 x1x UNALLOCATED
0 10 SME2 single-multi shift four registers
0 11 000 SME2 single-multi add four registers
0 11 != 000 UNALLOCATED
1 00 000 SME2 single-multi signed saturating doubling multiply high four registers
1 00 001 UNALLOCATED
1 != 00 UNALLOCATED
00 != 00x UNALLOCATED

SME2 single-multi int min/max four registers

These instructions are under SME2 Multi-vector - Multiple and Single SVE Destructive (Four registers).

313029282726252423222120191817161514131211109876543210
11000001size10Zm1010100000opZdn0U
Decode fields Instruction Details Feature
op U
0 0 SMAX (multiple and single vector)FEAT_SME2
0 1 UMAX (multiple and single vector)FEAT_SME2
1 0 SMIN (multiple and single vector)FEAT_SME2
1 1 UMIN (multiple and single vector)FEAT_SME2

SME2 single-multi FP min/max four registers

These instructions are under SME2 Multi-vector - Multiple and Single SVE Destructive (Four registers).

313029282726252423222120191817161514131211109876543210
11000001size10Zm1010100100opZdn0o2
Decode fields Instruction Details Feature
size op o2
!= 00 0 0 FMAX (multiple and single vector)FEAT_SME2
!= 00 0 1 FMIN (multiple and single vector)FEAT_SME2
!= 00 1 0 FMAXNM (multiple and single vector)FEAT_SME2
!= 00 1 1 FMINNM (multiple and single vector)FEAT_SME2
00 0 0 BFMAX (multiple and single vector)FEAT_SVE_B16B16
00 0 1 BFMIN (multiple and single vector)FEAT_SVE_B16B16
00 1 0 BFMAXNM (multiple and single vector)FEAT_SVE_B16B16
00 1 1 BFMINNM (multiple and single vector)FEAT_SVE_B16B16

SME2 multiple and single vector FSCALE four registers

These instructions are under SME2 Multi-vector - Multiple and Single SVE Destructive (Four registers).

313029282726252423222120191817161514131211109876543210
11000001size10Zm10101001100Zdn0op
Decode fields Instruction Details Feature
op
0 FSCALE (multiple and single vector)FEAT_FP8
1 UNALLOCATED-

SME2 single-multi shift four registers

These instructions are under SME2 Multi-vector - Multiple and Single SVE Destructive (Four registers).

313029282726252423222120191817161514131211109876543210
11000001size10Zm10101010opcZdn0U
Decode fields Instruction Details Feature
opc U
000 UNALLOCATED-
001 0 SRSHL (multiple and single vector)FEAT_SME2
001 1 URSHL (multiple and single vector)FEAT_SME2
01x UNALLOCATED-
1xx UNALLOCATED-

SME2 single-multi add four registers

These instructions are under SME2 Multi-vector - Multiple and Single SVE Destructive (Four registers).

313029282726252423222120191817161514131211109876543210
11000001size10Zm10101011000Zdn0op
Decode fields Instruction Details Feature
op
0 ADD (to vector)FEAT_SME2
1 UNALLOCATED-

SME2 single-multi signed saturating doubling multiply high four registers

These instructions are under SME2 Multi-vector - Multiple and Single SVE Destructive (Four registers).

313029282726252423222120191817161514131211109876543210
11000001size10Zm10101100000Zdn0op
Decode fields Instruction Details Feature
op
0 SQDMULH (multiple and single vector)FEAT_SME2
1 UNALLOCATED-

SME2 Multi-vector - Multiple and Single Array Vectors (Two registers)

These instructions are under SME encodings.

313029282726252423222120191817161514131211109876543210
110000010op0100op1op2op3
Decode fieldsInstruction detailsFeature
op0op1op2op3
0 000 000 1 FMLALL (multiple and single vector)Two ZA quad-vectorsFEAT_SME_F8F32
0 000 != 000 1 UNALLOCATED-
0 010 SME2 single-multi long FMA two sources-
0 011 SME2 multiple and single vector long FMA one source-
0 100 SME2 single-multi FP dot product two registers-
0 101 x1x SME2 single-multi mixed dot product two registers-
1 000 1 UNALLOCATED-
1 010 SME2 single-multi long MLA two sources-
1 011 SME2 multiple and single vector long MLA one source-
1 100 UNALLOCATED-
1 101 x1x SME2 single-multi two-way dot product two registers-
000 0 SME2 single-multi long long MLA two sources-
001 SME2 multiple and single vector long long FMA one source-
101 x0x SME2 single-multi four-way dot product two registers-
110 0xx SME2 single-multi ternary FP two registers-
110 1xx SME2 single-multi ternary int two registers-
111 0xx SME2 single-multi ternary FP16 two registers-
111 1xx UNALLOCATED-

SME2 single-multi long FMA two sources

These instructions are under SME2 Multi-vector - Multiple and Single Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
110000010010Zm0Rv010ZnopSo2off2
Decode fields Instruction Details Feature
op S o2
0 0 0 FMLAL (multiple and single vector, FP16 to FP32)FEAT_SME2
0 0 1 FMLAL (multiple and single vector, FP8 to FP16)FEAT_SME_F8F16
0 1 0 FMLSL (multiple and single vector)FEAT_SME2
0 1 1 UNALLOCATED-
1 1 UNALLOCATED-
1 0 0 BFMLAL (multiple and single vector)FEAT_SME2
1 1 0 BFMLSL (multiple and single vector)FEAT_SME2

SME2 multiple and single vector long FMA one source

These instructions are under SME2 Multi-vector - Multiple and Single Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
110000010010Zm0Rv011ZnopSoff3
Decode fields Instruction Details Feature
op S
0 0 FMLAL (multiple and single vector, FP16 to FP32)FEAT_SME2
0 1 FMLSL (multiple and single vector)FEAT_SME2
1 0 BFMLAL (multiple and single vector)FEAT_SME2
1 1 BFMLSL (multiple and single vector)FEAT_SME2

SME2 single-multi FP dot product two registers

These instructions are under SME2 Multi-vector - Multiple and Single Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
110000010010Zm0Rv100Znopcoff3
Decode fields Instruction Details Feature
opc
00 FDOT (2-way, multiple and single vector, FP16 to FP32)FEAT_SME2
01 FDOT (2-way, multiple and single vector, FP8 to FP16)FEAT_SME_F8F16
10 BFDOT (multiple and single vector)FEAT_SME2
11 FDOT (4-way, multiple and single vector)FEAT_SME_F8F32

SME2 single-multi mixed dot product two registers

These instructions are under SME2 Multi-vector - Multiple and Single Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
110000010010Zm0Rv101ZnU1off3
Decode fields Instruction Details Feature
U
0 USDOT (multiple and single vector)FEAT_SME2
1 SUDOT (multiple and single vector)FEAT_SME2

SME2 single-multi long MLA two sources

These instructions are under SME2 Multi-vector - Multiple and Single Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
110000010110Zm0Rv010ZnUSopoff2
Decode fields Instruction Details Feature
U S op
1 UNALLOCATED-
0 0 0 SMLAL (multiple and single vector)FEAT_SME2
0 1 0 SMLSL (multiple and single vector)FEAT_SME2
1 0 0 UMLAL (multiple and single vector)FEAT_SME2
1 1 0 UMLSL (multiple and single vector)FEAT_SME2

SME2 multiple and single vector long MLA one source

These instructions are under SME2 Multi-vector - Multiple and Single Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
110000010110Zm0Rv011ZnUSoff3
Decode fields Instruction Details Feature
U S
0 0 SMLAL (multiple and single vector)FEAT_SME2
0 1 SMLSL (multiple and single vector)FEAT_SME2
1 0 UMLAL (multiple and single vector)FEAT_SME2
1 1 UMLSL (multiple and single vector)FEAT_SME2

SME2 single-multi two-way dot product two registers

These instructions are under SME2 Multi-vector - Multiple and Single Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
110000010110Zm0Rv101ZnU1off3
Decode fields Instruction Details Feature
U
0 SDOT (2-way, multiple and single vector)FEAT_SME2
1 UDOT (2-way, multiple and single vector)FEAT_SME2

SME2 single-multi long long MLA two sources

These instructions are under SME2 Multi-vector - Multiple and Single Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
110000010sz10Zm0Rv000ZnUSop0o1
Decode fields Instruction Details Feature
sz U S op
0 0 0 SMLALL (multiple and single vector)FEAT_SME2
0 1 0 SMLSLL (multiple and single vector)FEAT_SME2
1 0 0 UMLALL (multiple and single vector)FEAT_SME2
1 1 0 UMLSLL (multiple and single vector)FEAT_SME2
0 1 1 UNALLOCATED-
0 0 0 1 USMLALL (multiple and single vector)FEAT_SME2
0 1 0 1 SUMLALL (multiple and single vector)FEAT_SME2
1 1 UNALLOCATED-

SME2 multiple and single vector long long FMA one source

These instructions are under SME2 Multi-vector - Multiple and Single Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
110000010sz10Zm0Rv001ZnUSopoff2
Decode fields Instruction Details Feature
sz U S op
0 0 0 SMLALL (multiple and single vector)FEAT_SME2
0 1 0 SMLSLL (multiple and single vector)FEAT_SME2
1 0 0 UMLALL (multiple and single vector)FEAT_SME2
1 1 0 UMLSLL (multiple and single vector)FEAT_SME2
0 0 0 1 USMLALL (multiple and single vector)FEAT_SME2
0 0 1 1 UNALLOCATED-
0 1 1 UNALLOCATED-
1 1 UNALLOCATED-

SME2 single-multi four-way dot product two registers

These instructions are under SME2 Multi-vector - Multiple and Single Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
110000010sz10Zm0Rv101ZnU0off3
Decode fields Instruction Details Feature
U
0 SDOT (4-way, multiple and single vector)FEAT_SME2
1 UDOT (4-way, multiple and single vector)FEAT_SME2

SME2 single-multi ternary FP two registers

These instructions are under SME2 Multi-vector - Multiple and Single Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
110000010sz10Zm0Rv110Zn0Soff3
Decode fields Instruction Details Feature
S
0 FMLA (multiple and single vector)FEAT_SME2
1 FMLS (multiple and single vector)FEAT_SME2

SME2 single-multi ternary int two registers

These instructions are under SME2 Multi-vector - Multiple and Single Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
110000010sz10Zm0Rv110Zn1Soff3
Decode fields Instruction Details Feature
S
0 ADD (array results, multiple and single vector)FEAT_SME2
1 SUB (array results, multiple and single vector)FEAT_SME2

SME2 single-multi ternary FP16 two registers

These instructions are under SME2 Multi-vector - Multiple and Single Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
110000010sz10Zm0Rv111Zn0Soff3
Decode fields Instruction Details Feature
sz S
0 0 FMLA (multiple and single vector)FEAT_SME_F16F16
0 1 FMLS (multiple and single vector)FEAT_SME_F16F16
1 0 BFMLA (multiple and single vector)FEAT_SVE_B16B16
1 1 BFMLS (multiple and single vector)FEAT_SVE_B16B16

SME2 Multi-vector - Multiple and Single Array Vectors (Four registers)

These instructions are under SME encodings.

313029282726252423222120191817161514131211109876543210
110000010op0110op1op2op3
Decode fieldsInstruction detailsFeature
op0op1op2op3
0 000 000 1 FMLALL (multiple and single vector)Four ZA quad-vectorsFEAT_SME_F8F32
0 000 != 000 1 UNALLOCATED-
0 001 000 FMLALL (multiple and single vector)One ZA quad-vectorFEAT_SME_F8F32
0 001 001 UNALLOCATED-
0 010 SME2 single-multi long FMA four sources-
0 011 00x FMLAL (multiple and single vector, FP8 to FP16)One ZA double-vectorFEAT_SME_F8F16
0 0x1 != 00x UNALLOCATED-
0 100 SME2 single-multi FP dot product four registers-
0 101 x1x SME2 single-multi mixed dot product four registers-
1 000 1 UNALLOCATED-
1 010 SME2 single-multi long MLA four sources-
1 0x1 UNALLOCATED-
1 100 UNALLOCATED-
1 101 x1x SME2 single-multi two-way dot product four registers-
000 0 SME2 single-multi long long MLA four sources-
101 x0x SME2 single-multi four-way dot product four registers-
110 0xx SME2 single-multi ternary FP four registers-
110 1xx SME2 single-multi ternary int four registers-
111 0xx SME2 single-multi ternary FP16 four registers-
111 1xx UNALLOCATED-

SME2 single-multi long FMA four sources

These instructions are under SME2 Multi-vector - Multiple and Single Array Vectors (Four registers).

313029282726252423222120191817161514131211109876543210
110000010011Zm0Rv010ZnopSo2off2
Decode fields Instruction Details Feature
op S o2
0 0 0 FMLAL (multiple and single vector, FP16 to FP32)FEAT_SME2
0 0 1 FMLAL (multiple and single vector, FP8 to FP16)FEAT_SME_F8F16
0 1 0 FMLSL (multiple and single vector)FEAT_SME2
0 1 1 UNALLOCATED-
1 1 UNALLOCATED-
1 0 0 BFMLAL (multiple and single vector)FEAT_SME2
1 1 0 BFMLSL (multiple and single vector)FEAT_SME2

SME2 single-multi FP dot product four registers

These instructions are under SME2 Multi-vector - Multiple and Single Array Vectors (Four registers).

313029282726252423222120191817161514131211109876543210
110000010011Zm0Rv100Znopcoff3
Decode fields Instruction Details Feature
opc
00 FDOT (2-way, multiple and single vector, FP16 to FP32)FEAT_SME2
01 FDOT (2-way, multiple and single vector, FP8 to FP16)FEAT_SME_F8F16
10 BFDOT (multiple and single vector)FEAT_SME2
11 FDOT (4-way, multiple and single vector)FEAT_SME_F8F32

SME2 single-multi mixed dot product four registers

These instructions are under SME2 Multi-vector - Multiple and Single Array Vectors (Four registers).

313029282726252423222120191817161514131211109876543210
110000010011Zm0Rv101ZnU1off3
Decode fields Instruction Details Feature
U
0 USDOT (multiple and single vector)FEAT_SME2
1 SUDOT (multiple and single vector)FEAT_SME2

SME2 single-multi long MLA four sources

These instructions are under SME2 Multi-vector - Multiple and Single Array Vectors (Four registers).

313029282726252423222120191817161514131211109876543210
110000010111Zm0Rv010ZnUSopoff2
Decode fields Instruction Details Feature
U S op
1 UNALLOCATED-
0 0 0 SMLAL (multiple and single vector)FEAT_SME2
0 1 0 SMLSL (multiple and single vector)FEAT_SME2
1 0 0 UMLAL (multiple and single vector)FEAT_SME2
1 1 0 UMLSL (multiple and single vector)FEAT_SME2

SME2 single-multi two-way dot product four registers

These instructions are under SME2 Multi-vector - Multiple and Single Array Vectors (Four registers).

313029282726252423222120191817161514131211109876543210
110000010111Zm0Rv101ZnU1off3
Decode fields Instruction Details Feature
U
0 SDOT (2-way, multiple and single vector)FEAT_SME2
1 UDOT (2-way, multiple and single vector)FEAT_SME2

SME2 single-multi long long MLA four sources

These instructions are under SME2 Multi-vector - Multiple and Single Array Vectors (Four registers).

313029282726252423222120191817161514131211109876543210
110000010sz11Zm0Rv000ZnUSop0o1
Decode fields Instruction Details Feature
sz U S op
0 0 0 SMLALL (multiple and single vector)FEAT_SME2
0 1 0 SMLSLL (multiple and single vector)FEAT_SME2
1 0 0 UMLALL (multiple and single vector)FEAT_SME2
1 1 0 UMLSLL (multiple and single vector)FEAT_SME2
0 1 1 UNALLOCATED-
0 0 0 1 USMLALL (multiple and single vector)FEAT_SME2
0 1 0 1 SUMLALL (multiple and single vector)FEAT_SME2
1 1 UNALLOCATED-

SME2 single-multi four-way dot product four registers

These instructions are under SME2 Multi-vector - Multiple and Single Array Vectors (Four registers).

313029282726252423222120191817161514131211109876543210
110000010sz11Zm0Rv101ZnU0off3
Decode fields Instruction Details Feature
U
0 SDOT (4-way, multiple and single vector)FEAT_SME2
1 UDOT (4-way, multiple and single vector)FEAT_SME2

SME2 single-multi ternary FP four registers

These instructions are under SME2 Multi-vector - Multiple and Single Array Vectors (Four registers).

313029282726252423222120191817161514131211109876543210
110000010sz11Zm0Rv110Zn0Soff3
Decode fields Instruction Details Feature
S
0 FMLA (multiple and single vector)FEAT_SME2
1 FMLS (multiple and single vector)FEAT_SME2

SME2 single-multi ternary int four registers

These instructions are under SME2 Multi-vector - Multiple and Single Array Vectors (Four registers).

313029282726252423222120191817161514131211109876543210
110000010sz11Zm0Rv110Zn1Soff3
Decode fields Instruction Details Feature
S
0 ADD (array results, multiple and single vector)FEAT_SME2
1 SUB (array results, multiple and single vector)FEAT_SME2

SME2 single-multi ternary FP16 four registers

These instructions are under SME2 Multi-vector - Multiple and Single Array Vectors (Four registers).

313029282726252423222120191817161514131211109876543210
110000010sz11Zm0Rv111Zn0Soff3
Decode fields Instruction Details Feature
sz S
0 0 FMLA (multiple and single vector)FEAT_SME_F16F16
0 1 FMLS (multiple and single vector)FEAT_SME_F16F16
1 0 BFMLA (multiple and single vector)FEAT_SVE_B16B16
1 1 BFMLS (multiple and single vector)FEAT_SVE_B16B16

SME2 Multi-vector - Multiple Array Vectors (Two registers)

These instructions are under SME encodings.

313029282726252423222120191817161514131211109876543210
110000011op01op1op200op3op4op5op6
Decode fieldsInstruction detailsFeature
op0op1op2op3op4op5op6
0 00 x0 11x 1 UNALLOCATED-
0 000 1 000 0 FMLALL (multiple vectors)Two ZA quad-vectorsFEAT_SME_F8F32
0 000 1 000 1 UNALLOCATED-
0 010 0 xx0 SME2 multiple vectors long FMA two sources-
0 010 1 000 FMLAL (multiple vectors, FP8 to FP16)Two ZA double-vectorsFEAT_SME_F8F16
0 0x0 1 != 000 UNALLOCATED-
0 100 1 x1x UNALLOCATED-
0 100 x0x SME2 multiple vectors FP dot product two registers-
0 101 0 01x USDOT (multiple vectors)Two ZA single-vectorsFEAT_SME2
0 101 0 11x UNALLOCATED-
0 101 1 UNALLOCATED-
1 00 x0 1xx 1 UNALLOCATED-
1 00 x1 10x 1 UNALLOCATED-
1 != 00 10x 1 UNALLOCATED-
1 010 0 xx0 SME2 multiple vectors long MLA two sources-
1 0x0 1 UNALLOCATED-
1 100 0 x0x UNALLOCATED-
1 101 0 x1x SME2 multiple vectors two-way dot product two registers-
00 00 111 0 0xx SME2 multiple vectors binary FP two registers-
00 00 111 0 1xx SME2 multiple vectors binary int two registers-
00 10 111 0 0xx SME2 multiple vectors binary FP16 two registers-
00 10 111 0 1xx UNALLOCATED-
00 x1 110 1 UNALLOCATED-
00 x1 111 UNALLOCATED-
!= 00 110 1 UNALLOCATED-
!= 00 111 UNALLOCATED-
000 0 0 SME2 multiple vectors long long MLA two sources-
000 0 1 UNALLOCATED-
010 0 xx1 UNALLOCATED-
0x1 UNALLOCATED-
100 0 x1x SME2 multiple vectors ternary FP16 two registers-
101 0 x0x SME2 multiple vectors four-way dot product two registers-
110 0 0xx SME2 multiple vectors ternary FP two registers-
110 0 1xx SME2 multiple vectors ternary int two registers-

SME2 multiple vectors long FMA two sources

These instructions are under SME2 Multi-vector - Multiple Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
11000001101Zm00Rv010Zn0opS0off2
Decode fields Instruction Details Feature
op S
0 0 FMLAL (multiple vectors, FP16 to FP32)FEAT_SME2
0 1 FMLSL (multiple vectors)FEAT_SME2
1 0 BFMLAL (multiple vectors)FEAT_SME2
1 1 BFMLSL (multiple vectors)FEAT_SME2

SME2 multiple vectors FP dot product two registers

These instructions are under SME2 Multi-vector - Multiple Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
11000001101Zm00Rv100Znopc0off3
Decode fields Instruction Details Feature
opc
00 FDOT (2-way, multiple vectors, FP16 to FP32)FEAT_SME2
01 BFDOT (multiple vectors)FEAT_SME2
10 FDOT (2-way, multiple vectors, FP8 to FP16)FEAT_SME_F8F16
11 FDOT (4-way, multiple vectors)FEAT_SME_F8F32

SME2 multiple vectors long MLA two sources

These instructions are under SME2 Multi-vector - Multiple Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
11000001111Zm00Rv010Zn0US0off2
Decode fields Instruction Details Feature
U S
0 0 SMLAL (multiple vectors)FEAT_SME2
0 1 SMLSL (multiple vectors)FEAT_SME2
1 0 UMLAL (multiple vectors)FEAT_SME2
1 1 UMLSL (multiple vectors)FEAT_SME2

SME2 multiple vectors two-way dot product two registers

These instructions are under SME2 Multi-vector - Multiple Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
11000001111Zm00Rv101Zn0U1off3
Decode fields Instruction Details Feature
U
0 SDOT (2-way, multiple vectors)FEAT_SME2
1 UDOT (2-way, multiple vectors)FEAT_SME2

SME2 multiple vectors binary FP two registers

These instructions are under SME2 Multi-vector - Multiple Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
110000011sz1000000Rv111Zm00Soff3
Decode fields Instruction Details Feature
S
0 FADDFEAT_SME2
1 FSUBFEAT_SME2

SME2 multiple vectors binary int two registers

These instructions are under SME2 Multi-vector - Multiple Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
110000011sz1000000Rv111Zm01Soff3
Decode fields Instruction Details Feature
S
0 ADD (array accumulators)FEAT_SME2
1 SUB (array accumulators)FEAT_SME2

SME2 multiple vectors binary FP16 two registers

These instructions are under SME2 Multi-vector - Multiple Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
110000011sz1001000Rv111Zm00Soff3
Decode fields Instruction Details Feature
sz S
0 0 FADDFEAT_SME_F16F16
0 1 FSUBFEAT_SME_F16F16
1 0 BFADDFEAT_SVE_B16B16
1 1 BFSUBFEAT_SVE_B16B16

SME2 multiple vectors long long MLA two sources

These instructions are under SME2 Multi-vector - Multiple Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
110000011sz1Zm00Rv000Zn0USop0o1
Decode fields Instruction Details Feature
sz U S op
0 0 0 SMLALL (multiple vectors)FEAT_SME2
0 1 0 SMLSLL (multiple vectors)FEAT_SME2
1 0 0 UMLALL (multiple vectors)FEAT_SME2
1 1 0 UMLSLL (multiple vectors)FEAT_SME2
0 0 0 1 USMLALL (multiple vectors)FEAT_SME2
0 0 1 1 UNALLOCATED-
0 1 1 UNALLOCATED-
1 1 UNALLOCATED-

SME2 multiple vectors ternary FP16 two registers

These instructions are under SME2 Multi-vector - Multiple Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
110000011sz1Zm00Rv100Zn0S1off3
Decode fields Instruction Details Feature
sz S
0 0 FMLA (multiple vectors)FEAT_SME_F16F16
0 1 FMLS (multiple vectors)FEAT_SME_F16F16
1 0 BFMLA (multiple vectors)FEAT_SVE_B16B16
1 1 BFMLS (multiple vectors)FEAT_SVE_B16B16

SME2 multiple vectors four-way dot product two registers

These instructions are under SME2 Multi-vector - Multiple Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
110000011sz1Zm00Rv101Zn0U0off3
Decode fields Instruction Details Feature
U
0 SDOT (4-way, multiple vectors)FEAT_SME2
1 UDOT (4-way, multiple vectors)FEAT_SME2

SME2 multiple vectors ternary FP two registers

These instructions are under SME2 Multi-vector - Multiple Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
110000011sz1Zm00Rv110Zn00Soff3
Decode fields Instruction Details Feature
S
0 FMLA (multiple vectors)FEAT_SME2
1 FMLS (multiple vectors)FEAT_SME2

SME2 multiple vectors ternary int two registers

These instructions are under SME2 Multi-vector - Multiple Array Vectors (Two registers).

313029282726252423222120191817161514131211109876543210
110000011sz1Zm00Rv110Zn01Soff3
Decode fields Instruction Details Feature
S
0 ADD (array results, multiple vectors)FEAT_SME2
1 SUB (array results, multiple vectors)FEAT_SME2

SME2 Multi-vector - Multiple Array Vectors (Four registers)

These instructions are under SME encodings.

313029282726252423222120191817161514131211109876543210
110000011op01op1op210op3op4op5op6
Decode fieldsInstruction detailsFeature
op0op1op2op3op4op5op6
0 00 x0 11x 01 UNALLOCATED-
0 x0 000 01 000 0 FMLALL (multiple vectors)Four ZA quad-vectorsFEAT_SME_F8F32
0 x0 000 01 000 1 UNALLOCATED-
0 x0 010 00 xx0 SME2 multiple vectors long FMA four sources-
0 x0 010 01 000 FMLAL (multiple vectors, FP8 to FP16)Four ZA double-vectorsFEAT_SME_F8F16
0 x0 0x0 01 != 000 UNALLOCATED-
0 x0 100 01 x1x UNALLOCATED-
0 x0 100 0x x0x SME2 multiple vectors FP dot product four registers-
0 x0 101 00 01x USDOT (multiple vectors)Four ZA single-vectorsFEAT_SME2
0 x0 101 00 11x UNALLOCATED-
0 x0 101 01 UNALLOCATED-
1 00 x0 1xx 01 UNALLOCATED-
1 != 00 x0 10x 01 UNALLOCATED-
1 x0 010 00 xx0 SME2 multiple vectors long MLA four sources-
1 x0 0x0 01 UNALLOCATED-
1 x0 100 00 x0x UNALLOCATED-
1 x0 101 00 x1x SME2 multiple vectors two-way dot product four registers-
00 00 111 00 0xx SME2 multiple vectors binary FP four registers-
00 00 111 00 1xx SME2 multiple vectors binary int four registers-
00 10 111 00 0xx SME2 multiple vectors binary FP16 four registers-
00 10 111 00 1xx UNALLOCATED-
00 x0 1xx 1x UNALLOCATED-
!= 00 x0 10x 1x UNALLOCATED-
!= 00 x0 110 01 UNALLOCATED-
!= 00 x0 110 1x UNALLOCATED-
!= 00 x0 111 UNALLOCATED-
x0 000 00 0 SME2 multiple vectors long long MLA four sources-
x0 000 00 1 UNALLOCATED-
x0 010 00 xx1 UNALLOCATED-
x0 0x0 1x UNALLOCATED-
x0 0x1 UNALLOCATED-
x0 100 00 x1x SME2 multiple vectors ternary FP16 four registers-
x0 101 00 x0x SME2 multiple vectors four-way dot product four registers-
x0 110 00 0xx SME2 multiple vectors ternary FP four registers-
x0 110 00 1xx SME2 multiple vectors ternary int four registers-
x1 UNALLOCATED-

SME2 multiple vectors long FMA four sources

These instructions are under SME2 Multi-vector - Multiple Array Vectors (Four registers).

313029282726252423222120191817161514131211109876543210
11000001101Zm010Rv010Zn00opS0off2
Decode fields Instruction Details Feature
op S
0 0 FMLAL (multiple vectors, FP16 to FP32)FEAT_SME2
0 1 FMLSL (multiple vectors)FEAT_SME2
1 0 BFMLAL (multiple vectors)FEAT_SME2
1 1 BFMLSL (multiple vectors)FEAT_SME2

SME2 multiple vectors FP dot product four registers

These instructions are under SME2 Multi-vector - Multiple Array Vectors (Four registers).

313029282726252423222120191817161514131211109876543210
11000001101Zm010Rv100Zn0opc0off3
Decode fields Instruction Details Feature
opc
00 FDOT (2-way, multiple vectors, FP16 to FP32)FEAT_SME2
01 BFDOT (multiple vectors)FEAT_SME2
10 FDOT (2-way, multiple vectors, FP8 to FP16)FEAT_SME_F8F16
11 FDOT (4-way, multiple vectors)FEAT_SME_F8F32

SME2 multiple vectors long MLA four sources

These instructions are under SME2 Multi-vector - Multiple Array Vectors (Four registers).

313029282726252423222120191817161514131211109876543210
11000001111Zm010Rv010Zn00US0off2
Decode fields Instruction Details Feature
U S
0 0 SMLAL (multiple vectors)FEAT_SME2
0 1 SMLSL (multiple vectors)FEAT_SME2
1 0 UMLAL (multiple vectors)FEAT_SME2
1 1 UMLSL (multiple vectors)FEAT_SME2

SME2 multiple vectors two-way dot product four registers

These instructions are under SME2 Multi-vector - Multiple Array Vectors (Four registers).

313029282726252423222120191817161514131211109876543210
11000001111Zm010Rv101Zn00U1off3
Decode fields Instruction Details Feature
U
0 SDOT (2-way, multiple vectors)FEAT_SME2
1 UDOT (2-way, multiple vectors)FEAT_SME2

SME2 multiple vectors binary FP four registers

These instructions are under SME2 Multi-vector - Multiple Array Vectors (Four registers).

313029282726252423222120191817161514131211109876543210
110000011sz1000010Rv111Zm000Soff3
Decode fields Instruction Details Feature
S
0 FADDFEAT_SME2
1 FSUBFEAT_SME2

SME2 multiple vectors binary int four registers

These instructions are under SME2 Multi-vector - Multiple Array Vectors (Four registers).

313029282726252423222120191817161514131211109876543210
110000011sz1000010Rv111Zm001Soff3
Decode fields Instruction Details Feature
S
0 ADD (array accumulators)FEAT_SME2
1 SUB (array accumulators)FEAT_SME2

SME2 multiple vectors binary FP16 four registers

These instructions are under SME2 Multi-vector - Multiple Array Vectors (Four registers).

313029282726252423222120191817161514131211109876543210
110000011sz1001010Rv111Zm000Soff3
Decode fields Instruction Details Feature
sz S
0 0 FADDFEAT_SME_F16F16
0 1 FSUBFEAT_SME_F16F16
1 0 BFADDFEAT_SVE_B16B16
1 1 BFSUBFEAT_SVE_B16B16

SME2 multiple vectors long long MLA four sources

These instructions are under SME2 Multi-vector - Multiple Array Vectors (Four registers).

313029282726252423222120191817161514131211109876543210
110000011sz1Zm010Rv000Zn00USop0o1
Decode fields Instruction Details Feature
sz U S op
0 0 0 SMLALL (multiple vectors)FEAT_SME2
0 1 0 SMLSLL (multiple vectors)FEAT_SME2
1 0 0 UMLALL (multiple vectors)FEAT_SME2
1 1 0 UMLSLL (multiple vectors)FEAT_SME2
0 0 0 1 USMLALL (multiple vectors)FEAT_SME2
0 0 1 1 UNALLOCATED-
0 1 1 UNALLOCATED-
1 1 UNALLOCATED-

SME2 multiple vectors ternary FP16 four registers

These instructions are under SME2 Multi-vector - Multiple Array Vectors (Four registers).

313029282726252423222120191817161514131211109876543210
110000011sz1Zm010Rv100Zn00S1off3
Decode fields Instruction Details Feature
sz S
0 0 FMLA (multiple vectors)FEAT_SME_F16F16
0 1 FMLS (multiple vectors)FEAT_SME_F16F16
1 0 BFMLA (multiple vectors)FEAT_SVE_B16B16
1 1 BFMLS (multiple vectors)FEAT_SVE_B16B16

SME2 multiple vectors four-way dot product four registers

These instructions are under SME2 Multi-vector - Multiple Array Vectors (Four registers).

313029282726252423222120191817161514131211109876543210
110000011sz1Zm010Rv101Zn00U0off3
Decode fields Instruction Details Feature
U
0 SDOT (4-way, multiple vectors)FEAT_SME2
1 UDOT (4-way, multiple vectors)FEAT_SME2

SME2 multiple vectors ternary FP four registers

These instructions are under SME2 Multi-vector - Multiple Array Vectors (Four registers).

313029282726252423222120191817161514131211109876543210
110000011sz1Zm010Rv110Zn000Soff3
Decode fields Instruction Details Feature
S
0 FMLA (multiple vectors)FEAT_SME2
1 FMLS (multiple vectors)FEAT_SME2

SME2 multiple vectors ternary int four registers

These instructions are under SME2 Multi-vector - Multiple Array Vectors (Four registers).

313029282726252423222120191817161514131211109876543210
110000011sz1Zm010Rv110Zn001Soff3
Decode fields Instruction Details Feature
S
0 ADD (array results, multiple vectors)FEAT_SME2
1 SUB (array results, multiple vectors)FEAT_SME2

SME Memory

These instructions are under SME encodings.

313029282726252423222120191817161514131211109876543210
1110000op0op1op2op3op4
Decode fieldsInstruction detailsFeature
op0op1op2op3op4
0xx0 0xx SME load array vector (elements)-
0xx1 0xx SME store array vector (elements)-
0xxx 1xx UNALLOCATED-
100x 00000 0 xx000 0xx SME save and restore array-
100x 00000 0 xx000 1xx UNALLOCATED-
100x 00000 0 xx!= 000 UNALLOCATED-
100x != 00000 0 UNALLOCATED-
100x 1 00000 000 SME2 lookup table load/store-
100x 1 00000 != 000 UNALLOCATED-
100x 1 != 00000 UNALLOCATED-
101x UNALLOCATED-
110x UNALLOCATED-
1110 0xx LD1QFEAT_SME
1111 0xx ST1QFEAT_SME
111x 1xx UNALLOCATED-

SME load array vector (elements)

These instructions are under SME Memory.

313029282726252423222120191817161514131211109876543210
11100000msz0RmVRsPgRn0opc
Decode fields Instruction Details Feature
msz
00 LD1B (scalar plus scalar, tile slice)FEAT_SME
01 LD1H (scalar plus scalar, tile slice)FEAT_SME
10 LD1W (scalar plus scalar, tile slice)FEAT_SME
11 LD1D (scalar plus scalar, tile slice)FEAT_SME

SME store array vector (elements)

These instructions are under SME Memory.

313029282726252423222120191817161514131211109876543210
11100000msz1RmVRsPgRn0opc
Decode fields Instruction Details Feature
msz
00 ST1B (scalar plus scalar, tile slice)FEAT_SME
01 ST1H (scalar plus scalar, tile slice)FEAT_SME
10 ST1W (scalar plus scalar, tile slice)FEAT_SME
11 ST1D (scalar plus scalar, tile slice)FEAT_SME

SME save and restore array

These instructions are under SME Memory.

313029282726252423222120191817161514131211109876543210
1110000100op000000Rv000Rn0imm4
Decode fields Instruction Details Feature
op
0 LDR (array vector)FEAT_SME
1 STR (array vector)FEAT_SME

SME2 lookup table load/store

These instructions are under SME Memory.

313029282726252423222120191817161514131211109876543210
1110000100opc100000Rn000opc2
Decode fields Instruction Details Feature
opc opc2
x0xxxx UNALLOCATED-
x10xxx UNALLOCATED-
x110xx UNALLOCATED-
x1110x UNALLOCATED-
x11110 UNALLOCATED-
x11111 01 UNALLOCATED-
x11111 1x UNALLOCATED-
011111 00 LDR (table)FEAT_SME2
111111 00 STR (table)FEAT_SME2

SVE encodings

These instructions are under the top-level.

313029282726252423222120191817161514131211109876543210
op00010op1op2op3
Decode fieldsInstruction detailsFeature
op0op1op2op3
000 0xx0xxxx x1xxxx SVE Integer Multiply-Add - Predicated-
000 0xx0xxxx 000xxx SVE Integer Binary Arithmetic - Predicated-
000 0xx0xxxx 001xxx SVE Integer Reduction-
000 0xx0xxxx 100xxx SVE Bitwise Shift - Predicated-
000 0xx0xxxx 101xxx SVE Integer Unary Arithmetic - Predicated-
000 0xx1xxxx 000xxx SVE integer add/subtract vectors (unpredicated)-
000 0xx1xxxx 001xxx SVE Bitwise Logical - Unpredicated-
000 0xx1xxxx 0100xx SVE Index Generation-
000 0xx1xxxx 0101xx SVE Stack Allocation-
000 0xx1xxxx 011xxx SVE2 Integer Multiply - Unpredicated-
000 0xx1xxxx 100xxx SVE Bitwise Shift - Unpredicated-
000 0xx1xxxx 1010xx SVE address generation-
000 0xx1xxxx 1011xx SVE Integer Misc - Unpredicated-
000 0xx1xxxx 11xxxx SVE Element Count-
000 1xx00xxx SVE Bitwise Immediate-
000 1xx01xxx SVE Integer Wide Immediate - Predicated-
000 1xx1xxxx 001000 DUP (indexed)-
000 1xx1xxxx 001001 SVE Permute Vector - One Source Quadwords-
000 1xx1xxxx 00101x SVE table lookup (three sources)-
000 1xx1xxxx 001100 TBLSVE-
000 1xx1xxxx 001101 TBXQFEAT_SVE2p1
000 1xx1xxxx 001110 SVE Permute Vector - Unpredicated-
000 1xx1xxxx 001111 UNALLOCATED-
000 1xx1xxxx 010xxx SVE Permute Predicate-
000 1xx1xxxx 011xxx SVE permute vector elements-
000 1xx1xxxx 10xxxx SVE Permute Vector - Predicated-
000 1xx1xxxx 11xxxx SEL (vectors)-
000 10x1xxxx 000xxx SVE Permute Vector - Extract-
000 11x1xxxx 000xxx SVE Permute Vector - Segments-
001 0xx0xxxx SVE Integer Compare - Vectors-
001 0xx1xxxx SVE integer compare with unsigned immediate-
001 1xx0xxxx x0xxxx SVE integer compare with signed immediate-
001 1xx00xxx 01xxxx SVE predicate logical operations-
001 1xx00xxx 11xxxx SVE Propagate Break-
001 1xx01xxx 01xxxx SVE Partition Break-
001 1xx01xxx 11xxxx SVE Predicate Misc-
001 1xx1xxxx 00xxxx SVE Integer Compare - Scalars-
001 1xx1xxxx 01xxxx 0 SVE broadcast predicate element-
001 1xx1xxxx 01xxxx 1 SVE Scalar Integer Compare - Predicate-as-counter-
001 1xx1xxxx 11xxxx SVE Integer Wide Immediate - Unpredicated-
001 1xx100xx 10xxxx SVE Predicate Count-
001 1xx101xx 1000xx SVE Inc/Dec by Predicate Count-
001 1xx101xx 1001xx SVE Write FFR-
001 1xx101xx 101xxx UNALLOCATED-
001 1xx11xxx 10xxxx UNALLOCATED-
010 0xx0xxxx 0xxxxx SVE Integer Multiply-Add - Unpredicated-
010 0xx0xxxx 10xxxx SVE2 Integer - Predicated-
010 0xx0xxxx 11000x SVE integer clamp-
010 0xx0xxxx 1101xx SVE2 multiply-add (checked pointer)-
010 0xx0xxxx 111xxx SVE permute vector elements (quadwords)-
010 0xx1xxxx SVE Multiply - Indexed-
010 0x10xxxx 11001x UNALLOCATED-
010 0000xxxx 11001x SVE two-way dot product-
010 0100xxxx 11001x SVE two-way dot product (indexed)-
010 1xx0xxxx 0xxxxx SVE2 Widening Integer Arithmetic-
010 1xx0xxxx 10xxxx SVE Misc-
010 1xx0xxxx 11xxxx SVE2 Accumulate-
010 1xx1xxxx 0xxxxx SVE2 Narrowing-
010 1xx1xxxx 100xxx SVE2 character match-
010 1xx1xxxx 101xxx SVE2 Histogram Computation (Segment) and Lookup Table-
010 1xx1xxxx 110xxx HISTCNT-
010 1xx1xxxx 111xxx SVE2 Crypto Extensions-
011 0xx0xxxx 0xxxxx FCMLA (vectors)-
011 0xx00x1x 1xxxxx UNALLOCATED-
011 0xx00000 100xxx FCADD-
011 0xx00000 101xxx UNALLOCATED-
011 0xx00000 11xxxx UNALLOCATED-
011 0xx00001 1xxxxx UNALLOCATED-
011 0xx0010x 100xxx UNALLOCATED-
011 0xx0010x 101xxx SVE floating-point convert precision odd elements-
011 0xx0010x 11xxxx UNALLOCATED-
011 0xx010xx 100xxx SVE2 floating-point pairwise operations-
011 0xx010xx 101xxx SVE floating-point recursive reduction (quadwords)-
011 0xx010xx 11xxxx UNALLOCATED-
011 0xx011xx 1xxxxx UNALLOCATED-
011 0xx1xxxx 0000xx SVE floating-point multiply-add (indexed)-
011 0xx1xxxx 0001xx SVE floating-point complex multiply-add (indexed)-
011 0xx1xxxx 0010x0 SVE floating-point multiply (indexed)-
011 0xx1xxxx 001001 SVE FP clamp-
011 0xx1xxxx 001011 UNALLOCATED-
011 0xx1xxxx 01x0xx SVE Floating Point Widening Multiply-Add - Indexed-
011 0xx1xxxx 10x00x SVE Floating Point Widening Multiply-Add-
011 0xx1xxxx 1100xx SVE2 FP8 multiply-add long long (indexed)-
011 0xx1xxxx 111000 UNALLOCATED-
011 0xx1xxxx 111001 SVE floating point matrix multiply accumulate-
011 0xx1xxxx 11101x UNALLOCATED-
011 0x01xxxx 0x11xx UNALLOCATED-
011 0x01xxxx 0101xx SVE2 FP8 multiply-add long (indexed)-
011 0x01xxxx 10xx10 SVE2 FP8 Widening Multiply-Add-
011 0x01xxxx 10xx11 UNALLOCATED-
011 0x01xxxx 10x10x UNALLOCATED-
011 0x01xxxx 11x1xx UNALLOCATED-
011 0x11xxxx 0011xx UNALLOCATED-
011 0x11xxxx 01x1xx UNALLOCATED-
011 0x11xxxx 1xx1xx UNALLOCATED-
011 0x11xxxx 10x01x UNALLOCATED-
011 1xx0xxxx x1xxxx SVE floating-point compare vectors-
011 1xx0xxxx 000xxx SVE floating-point arithmetic (unpredicated)-
011 1xx0xxxx 100xxx SVE Floating Point Arithmetic - Predicated-
011 1xx0xxxx 101xxx SVE Floating Point Unary Operations - Predicated-
011 1xx000xx 001xxx SVE floating-point recursive reduction-
011 1xx001xx 0010xx UNALLOCATED-
011 1xx001xx 0011xx SVE Floating Point Unary Operations - Unpredicated-
011 1xx010xx 001xxx SVE Floating Point Compare - with Zero-
011 1xx011xx 001xxx SVE Floating Point Accumulating Reduction-
011 1xx1xxxx SVE Floating Point Multiply-Add-
100 SVE Memory - 32-bit Gather and Unsized Contiguous-
101 SVE Memory - Contiguous Load-
110 SVE Memory - 64-bit Gather-
111 0x0xxx SVE Memory - Contiguous Store and Unsized Contiguous-
111 001xxx SVE Memory - Non-temporal and Quadword Scatter Store-
111 011xxx SVE Memory - Non-temporal and Multi-register Contiguous Store-
111 1x0xxx SVE Memory - Scatter with Optional Sign Extend-
111 101xxx SVE Memory - Scatter-
111 111xxx SVE Memory - Contiguous Store with Immediate Offset-

SVE Integer Multiply-Add - Predicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
000001000op01
Decode fieldsInstruction details
op0
0 SVE integer multiply-accumulate writing addend (predicated)
1 SVE integer multiply-add writing multiplicand (predicated)

SVE integer multiply-accumulate writing addend (predicated)

These instructions are under SVE Integer Multiply-Add - Predicated.

313029282726252423222120191817161514131211109876543210
00000100size0Zm01opPgZnZda
Decode fields Instruction Details
op
0 MLA (vectors)
1 MLS (vectors)

SVE integer multiply-add writing multiplicand (predicated)

These instructions are under SVE Integer Multiply-Add - Predicated.

313029282726252423222120191817161514131211109876543210
00000100size0Zm11opPgZaZdn
Decode fields Instruction Details
op
0 MAD
1 MSB

SVE Integer Binary Arithmetic - Predicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
000001000op0000
Decode fieldsInstruction details
op0
00x SVE integer add/subtract vectors (predicated)
01x SVE integer min/max/difference (predicated)
100 SVE integer multiply vectors (predicated)
101 SVE integer divide vectors (predicated)
11x SVE bitwise logical operations (predicated)

SVE integer add/subtract vectors (predicated)

These instructions are under SVE Integer Binary Arithmetic - Predicated.

313029282726252423222120191817161514131211109876543210
00000100size000opc000PgZmZdn
Decode fields Instruction Details Feature
size opc
000 ADD (vectors, predicated)-
001 SUB (vectors, predicated)-
010 UNALLOCATED-
011 SUBR (vectors)-
0x 1xx UNALLOCATED-
10 1xx UNALLOCATED-
11 100 ADDPT (predicated)FEAT_CPA
11 101 SUBPT (predicated)FEAT_CPA
11 11x UNALLOCATED-

SVE integer min/max/difference (predicated)

These instructions are under SVE Integer Binary Arithmetic - Predicated.

313029282726252423222120191817161514131211109876543210
00000100size001opcU000PgZmZdn
Decode fields Instruction Details
opc U
00 0 SMAX (vectors)
00 1 UMAX (vectors)
01 0 SMIN (vectors)
01 1 UMIN (vectors)
10 0 SABD
10 1 UABD
11 UNALLOCATED

SVE integer multiply vectors (predicated)

These instructions are under SVE Integer Binary Arithmetic - Predicated.

313029282726252423222120191817161514131211109876543210
00000100size0100HU000PgZmZdn
Decode fields Instruction Details
H U
0 0 MUL (vectors, predicated)
0 1 UNALLOCATED
1 0 SMULH (predicated)
1 1 UMULH (predicated)

SVE integer divide vectors (predicated)

These instructions are under SVE Integer Binary Arithmetic - Predicated.

313029282726252423222120191817161514131211109876543210
00000100size0101RU000PgZmZdn
Decode fields Instruction Details
R U
0 0 SDIV
0 1 UDIV
1 0 SDIVR
1 1 UDIVR

SVE bitwise logical operations (predicated)

These instructions are under SVE Integer Binary Arithmetic - Predicated.

313029282726252423222120191817161514131211109876543210
00000100size011opc000PgZmZdn
Decode fields Instruction Details
opc
000 ORR (vectors, predicated)
001 EOR (vectors, predicated)
010 AND (vectors, predicated)
011 BIC (vectors, predicated)
1xx UNALLOCATED

SVE Integer Reduction

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
000001000op0001
Decode fieldsInstruction details
op0
000 SVE integer add reduction (predicated)
001 SVE integer add reduction (quadwords)
010 SVE integer min/max reduction (predicated)
011 SVE integer min/max reduction (quadwords)
10x SVE constructive prefix (predicated)
110 SVE bitwise logical reduction (predicated)
111 SVE bitwise logical reduction (quadwords)

SVE integer add reduction (predicated)

These instructions are under SVE Integer Reduction.

313029282726252423222120191817161514131211109876543210
00000100size0000opU001PgZnVd
Decode fields Instruction Details
op U
0 0 SADDV
0 1 UADDV
1 UNALLOCATED

SVE integer add reduction (quadwords)

These instructions are under SVE Integer Reduction.

313029282726252423222120191817161514131211109876543210
00000100size0001opU001PgZnVd
Decode fields Instruction Details Feature
op U
0 0 UNALLOCATED-
0 1 ADDQVFEAT_SVE2p1
1 UNALLOCATED-

SVE integer min/max reduction (predicated)

These instructions are under SVE Integer Reduction.

313029282726252423222120191817161514131211109876543210
00000100size0010opU001PgZnVd
Decode fields Instruction Details
op U
0 0 SMAXV
0 1 UMAXV
1 0 SMINV
1 1 UMINV

SVE integer min/max reduction (quadwords)

These instructions are under SVE Integer Reduction.

313029282726252423222120191817161514131211109876543210
00000100size0011opU001PgZnVd
Decode fields Instruction Details Feature
op U
0 0 SMAXQVFEAT_SVE2p1
0 1 UMAXQVFEAT_SVE2p1
1 0 SMINQVFEAT_SVE2p1
1 1 UMINQVFEAT_SVE2p1

SVE constructive prefix (predicated)

These instructions are under SVE Integer Reduction.

313029282726252423222120191817161514131211109876543210
00000100size010opcM001PgZnZd
Decode fields Instruction Details
opc
00 MOVPRFX (predicated)
01 UNALLOCATED
1x UNALLOCATED

SVE bitwise logical reduction (predicated)

These instructions are under SVE Integer Reduction.

313029282726252423222120191817161514131211109876543210
00000100size0110opc001PgZnVd
Decode fields Instruction Details
opc
00 ORV
01 EORV
10 ANDV
11 UNALLOCATED

SVE bitwise logical reduction (quadwords)

These instructions are under SVE Integer Reduction.

313029282726252423222120191817161514131211109876543210
00000100size0111opc001PgZnVd
Decode fields Instruction Details Feature
opc
00 ORQVFEAT_SVE2p1
01 EORQVFEAT_SVE2p1
10 ANDQVFEAT_SVE2p1
11 UNALLOCATED-

SVE Bitwise Shift - Predicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
000001000op0100
Decode fieldsInstruction details
op0
0x SVE bitwise shift by immediate (predicated)
10 SVE bitwise shift by vector (predicated)
11 SVE bitwise shift by wide elements (predicated)

SVE bitwise shift by immediate (predicated)

These instructions are under SVE Bitwise Shift - Predicated.

313029282726252423222120191817161514131211109876543210
00000100tszh00opcLU100Pgtszlimm3Zdn
Decode fields Instruction Details
opc L U
00 0 0 ASR (immediate, predicated)
00 0 1 LSR (immediate, predicated)
00 1 0 UNALLOCATED
00 1 1 LSL (immediate, predicated)
01 0 0 ASRD
01 0 1 UNALLOCATED
01 1 0 SQSHL (immediate)
01 1 1 UQSHL (immediate)
10 UNALLOCATED
11 0 0 SRSHR
11 0 1 URSHR
11 1 0 UNALLOCATED
11 1 1 SQSHLU

SVE bitwise shift by vector (predicated)

These instructions are under SVE Bitwise Shift - Predicated.

313029282726252423222120191817161514131211109876543210
00000100size010RLU100PgZmZdn
Decode fields Instruction Details
R L U
1 0 UNALLOCATED
0 0 0 ASR (vectors)
0 0 1 LSR (vectors)
0 1 1 LSL (vectors)
1 0 0 ASRR
1 0 1 LSRR
1 1 1 LSLR

SVE bitwise shift by wide elements (predicated)

These instructions are under SVE Bitwise Shift - Predicated.

313029282726252423222120191817161514131211109876543210
00000100size011RLU100PgZmZdn
Decode fields Instruction Details
R L U
0 0 0 ASR (wide elements, predicated)
0 0 1 LSR (wide elements, predicated)
0 1 0 UNALLOCATED
0 1 1 LSL (wide elements, predicated)
1 UNALLOCATED

SVE Integer Unary Arithmetic - Predicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
000001000op0101
Decode fieldsInstruction details
op0
0x UNALLOCATED
10 SVE integer unary operations (predicated)
11 SVE bitwise unary operations (predicated)

SVE integer unary operations (predicated)

These instructions are under SVE Integer Unary Arithmetic - Predicated.

313029282726252423222120191817161514131211109876543210
00000100size010opc101PgZnZd
Decode fields Instruction Details
opc
000 SXTB, SXTH, SXTWSXTB
001 UXTB, UXTH, UXTWUXTB
010 SXTB, SXTH, SXTWSXTH
011 UXTB, UXTH, UXTWUXTH
100 SXTB, SXTH, SXTWSXTW
101 UXTB, UXTH, UXTWUXTW
110 ABS
111 NEG

SVE bitwise unary operations (predicated)

These instructions are under SVE Integer Unary Arithmetic - Predicated.

313029282726252423222120191817161514131211109876543210
00000100size011opc101PgZnZd
Decode fields Instruction Details
opc
000 CLS
001 CLZ
010 CNT
011 CNOT
100 FABS
101 FNEG
110 NOT (vector)
111 UNALLOCATED

SVE integer add/subtract vectors (unpredicated)

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
00000100size1Zm000opcZnZd
Decode fields Instruction Details Feature
size opc
000 ADD (vectors, unpredicated)-
001 SUB (vectors, unpredicated)-
100 SQADD (vectors, unpredicated)-
101 UQADD (vectors, unpredicated)-
110 SQSUB (vectors, unpredicated)-
111 UQSUB (vectors, unpredicated)-
0x 01x UNALLOCATED-
10 01x UNALLOCATED-
11 010 ADDPT (unpredicated)FEAT_CPA
11 011 SUBPT (unpredicated)FEAT_CPA

SVE Bitwise Logical - Unpredicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
000001001001op0
Decode fieldsInstruction details
op0
0xx UNALLOCATED
100 SVE bitwise logical operations (unpredicated)
101 XAR
11x SVE2 bitwise ternary operations

SVE bitwise logical operations (unpredicated)

These instructions are under SVE Bitwise Logical - Unpredicated.

313029282726252423222120191817161514131211109876543210
00000100opc1Zm001100ZnZd
Decode fields Instruction Details
opc
00 AND (vectors, unpredicated)
01 ORR (vectors, unpredicated)
10 EOR (vectors, unpredicated)
11 BIC (vectors, unpredicated)

SVE2 bitwise ternary operations

These instructions are under SVE Bitwise Logical - Unpredicated.

313029282726252423222120191817161514131211109876543210
00000100opc1Zm00111o2ZkZdn
Decode fields Instruction Details
opc o2
00 0 EOR3
00 1 BSL
01 0 BCAX
01 1 BSL1N
1x 0 UNALLOCATED
10 1 BSL2N
11 1 NBSL

SVE Index Generation

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
0000010010100op0
Decode fieldsInstruction details
op0
00 INDEX (immediates)
01 INDEX (scalar, immediate)
10 INDEX (immediate, scalar)
11 INDEX (scalars)

SVE Stack Allocation

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
00000100op010101op1
Decode fieldsInstruction details
op0op1
0 0 SVE stack frame adjustment
0 1 Streaming SVE stack frame adjustment
1 0 SVE stack frame size
1 1 Streaming SVE stack frame size

SVE stack frame adjustment

These instructions are under SVE Stack Allocation.

313029282726252423222120191817161514131211109876543210
000001000op1Rn01010imm6Rd
Decode fields Instruction Details
op
0 ADDVL
1 ADDPL

Streaming SVE stack frame adjustment

These instructions are under SVE Stack Allocation.

313029282726252423222120191817161514131211109876543210
000001000op1Rn01011imm6Rd
Decode fields Instruction Details Feature
op
0 ADDSVLFEAT_SME
1 ADDSPLFEAT_SME

SVE stack frame size

These instructions are under SVE Stack Allocation.

313029282726252423222120191817161514131211109876543210
000001001op1opc201010imm6Rd
Decode fields Instruction Details
op opc2
0 0xxxx UNALLOCATED
0 10xxx UNALLOCATED
0 110xx UNALLOCATED
0 1110x UNALLOCATED
0 11110 UNALLOCATED
0 11111 RDVL
1 UNALLOCATED

Streaming SVE stack frame size

These instructions are under SVE Stack Allocation.

313029282726252423222120191817161514131211109876543210
000001001op1opc201011imm6Rd
Decode fields Instruction Details Feature
op opc2
0 0xxxx UNALLOCATED-
0 10xxx UNALLOCATED-
0 110xx UNALLOCATED-
0 1110x UNALLOCATED-
0 11110 UNALLOCATED-
0 11111 RDSVLFEAT_SME
1 UNALLOCATED-

SVE2 Integer Multiply - Unpredicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
000001001011op0
Decode fieldsInstruction details
op0
0x SVE2 integer multiply vectors (unpredicated)
10 SVE2 signed saturating doubling multiply high (unpredicated)
11 UNALLOCATED

SVE2 integer multiply vectors (unpredicated)

These instructions are under SVE2 Integer Multiply - Unpredicated.

313029282726252423222120191817161514131211109876543210
00000100size1Zm0110opcZnZd
Decode fields Instruction Details
size opc
00 MUL (vectors, unpredicated)
10 SMULH (unpredicated)
11 UMULH (unpredicated)
00 01 PMUL
01 01 UNALLOCATED
1x 01 UNALLOCATED

SVE2 signed saturating doubling multiply high (unpredicated)

These instructions are under SVE2 Integer Multiply - Unpredicated.

313029282726252423222120191817161514131211109876543210
00000100size1Zm01110RZnZd
Decode fields Instruction Details
R
0 SQDMULH (vectors)
1 SQRDMULH (vectors)

SVE Bitwise Shift - Unpredicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
000001001100op0
Decode fieldsInstruction details
op0
0 SVE bitwise shift by wide elements (unpredicated)
1 SVE bitwise shift by immediate (unpredicated)

SVE bitwise shift by wide elements (unpredicated)

These instructions are under SVE Bitwise Shift - Unpredicated.

313029282726252423222120191817161514131211109876543210
00000100size1Zm1000opcZnZd
Decode fields Instruction Details
opc
00 ASR (wide elements, unpredicated)
01 LSR (wide elements, unpredicated)
10 UNALLOCATED
11 LSL (wide elements, unpredicated)

SVE bitwise shift by immediate (unpredicated)

These instructions are under SVE Bitwise Shift - Unpredicated.

313029282726252423222120191817161514131211109876543210
00000100tszh1tszlimm31001opcZnZd
Decode fields Instruction Details
opc
00 ASR (immediate, unpredicated)
01 LSR (immediate, unpredicated)
10 UNALLOCATED
11 LSL (immediate, unpredicated)

SVE address generation

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
00000100opc1Zm1010mszZnZd
Decode fields Instruction Details
opc
00 ADRUnpacked 32-bit signed offsets
01 ADRUnpacked 32-bit unsigned offsets
1x ADRPacked offsets

SVE Integer Misc - Unpredicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
0000010011011op0
Decode fieldsInstruction details
op0
0x SVE floating-point trig select coefficient
10 SVE floating-point exponential accelerator
11 SVE constructive prefix (unpredicated)

SVE floating-point trig select coefficient

These instructions are under SVE Integer Misc - Unpredicated.

313029282726252423222120191817161514131211109876543210
00000100size1Zm10110opZnZd
Decode fields Instruction Details
op
0 FTSSEL
1 UNALLOCATED

SVE floating-point exponential accelerator

These instructions are under SVE Integer Misc - Unpredicated.

313029282726252423222120191817161514131211109876543210
00000100size1opc101110ZnZd
Decode fields Instruction Details
opc
00000 FEXPA
00001 UNALLOCATED
0001x UNALLOCATED
001xx UNALLOCATED
01xxx UNALLOCATED
1xxxx UNALLOCATED

SVE constructive prefix (unpredicated)

These instructions are under SVE Integer Misc - Unpredicated.

313029282726252423222120191817161514131211109876543210
00000100opc1opc2101111ZnZd
Decode fields Instruction Details
opc opc2
00 00000 MOVPRFX (unpredicated)
00 00001 UNALLOCATED
00 0001x UNALLOCATED
00 001xx UNALLOCATED
00 01xxx UNALLOCATED
00 1xxxx UNALLOCATED
01 UNALLOCATED
1x UNALLOCATED

SVE Element Count

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
000001001op011op1
Decode fieldsInstruction details
op0op1
0 00x SVE saturating inc/dec vector by element count
0 100 SVE element count
0 101 UNALLOCATED
1 000 SVE inc/dec vector by element count
1 100 SVE inc/dec register by element count
1 x01 UNALLOCATED
01x UNALLOCATED
11x SVE saturating inc/dec register by element count

SVE saturating inc/dec vector by element count

These instructions are under SVE Element Count.

313029282726252423222120191817161514131211109876543210
00000100size10imm41100DUpatternZdn
Decode fields Instruction Details
size D U
00 UNALLOCATED
01 0 0 SQINCH (vector)
01 0 1 UQINCH (vector)
01 1 0 SQDECH (vector)
01 1 1 UQDECH (vector)
10 0 0 SQINCW (vector)
10 0 1 UQINCW (vector)
10 1 0 SQDECW (vector)
10 1 1 UQDECW (vector)
11 0 0 SQINCD (vector)
11 0 1 UQINCD (vector)
11 1 0 SQDECD (vector)
11 1 1 UQDECD (vector)

SVE element count

These instructions are under SVE Element Count.

313029282726252423222120191817161514131211109876543210
00000100size10imm411100oppatternRd
Decode fields Instruction Details
size op
1 UNALLOCATED
00 0 CNTB, CNTD, CNTH, CNTWCNTB
01 0 CNTB, CNTD, CNTH, CNTWCNTH
10 0 CNTB, CNTD, CNTH, CNTWCNTW
11 0 CNTB, CNTD, CNTH, CNTWCNTD

SVE inc/dec vector by element count

These instructions are under SVE Element Count.

313029282726252423222120191817161514131211109876543210
00000100size11imm411000DpatternZdn
Decode fields Instruction Details
size D
00 UNALLOCATED
01 0 INCD, INCH, INCW (vector)INCH
01 1 DECD, DECH, DECW (vector)DECH
10 0 INCD, INCH, INCW (vector)INCW
10 1 DECD, DECH, DECW (vector)DECW
11 0 INCD, INCH, INCW (vector)INCD
11 1 DECD, DECH, DECW (vector)DECD

SVE inc/dec register by element count

These instructions are under SVE Element Count.

313029282726252423222120191817161514131211109876543210
00000100size11imm411100DpatternRdn
Decode fields Instruction Details
size D
00 0 INCB, INCD, INCH, INCW (scalar)INCB
00 1 DECB, DECD, DECH, DECW (scalar)DECB
01 0 INCB, INCD, INCH, INCW (scalar)INCH
01 1 DECB, DECD, DECH, DECW (scalar)DECH
10 0 INCB, INCD, INCH, INCW (scalar)INCW
10 1 DECB, DECD, DECH, DECW (scalar)DECW
11 0 INCB, INCD, INCH, INCW (scalar)INCD
11 1 DECB, DECD, DECH, DECW (scalar)DECD

SVE saturating inc/dec register by element count

These instructions are under SVE Element Count.

313029282726252423222120191817161514131211109876543210
00000100size1sfimm41111DUpatternRdn
Decode fields Instruction Details
size sf D U
00 0 0 0 SQINCB32-bit
00 0 0 1 UQINCB32-bit
00 0 1 0 SQDECB32-bit
00 0 1 1 UQDECB32-bit
00 1 0 0 SQINCB64-bit
00 1 0 1 UQINCB64-bit
00 1 1 0 SQDECB64-bit
00 1 1 1 UQDECB64-bit
01 0 0 0 SQINCH (scalar)32-bit
01 0 0 1 UQINCH (scalar)32-bit
01 0 1 0 SQDECH (scalar)32-bit
01 0 1 1 UQDECH (scalar)32-bit
01 1 0 0 SQINCH (scalar)64-bit
01 1 0 1 UQINCH (scalar)64-bit
01 1 1 0 SQDECH (scalar)64-bit
01 1 1 1 UQDECH (scalar)64-bit
10 0 0 0 SQINCW (scalar)32-bit
10 0 0 1 UQINCW (scalar)32-bit
10 0 1 0 SQDECW (scalar)32-bit
10 0 1 1 UQDECW (scalar)32-bit
10 1 0 0 SQINCW (scalar)64-bit
10 1 0 1 UQINCW (scalar)64-bit
10 1 1 0 SQDECW (scalar)64-bit
10 1 1 1 UQDECW (scalar)64-bit
11 0 0 0 SQINCD (scalar)32-bit
11 0 0 1 UQINCD (scalar)32-bit
11 0 1 0 SQDECD (scalar)32-bit
11 0 1 1 UQDECD (scalar)32-bit
11 1 0 0 SQINCD (scalar)64-bit
11 1 0 1 UQINCD (scalar)64-bit
11 1 1 0 SQDECD (scalar)64-bit
11 1 1 1 UQDECD (scalar)64-bit

SVE Bitwise Immediate

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
00000101op000op1
Decode fieldsInstruction details
op0op1
11 00 DUPM
!= 11 00 SVE bitwise logical with immediate (unpredicated)
!= 00 UNALLOCATED

SVE bitwise logical with immediate (unpredicated)

These instructions are under SVE Bitwise Immediate.

313029282726252423222120191817161514131211109876543210
00000101!= 110000imm13Zdn
opc

The following constraints also apply to this encoding: opc != 11 && opc != 11

Decode fields Instruction Details
opc
00 ORR (immediate)
01 EOR (immediate)
10 AND (immediate)

SVE Integer Wide Immediate - Predicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
0000010101op0
Decode fieldsInstruction details
op0
0xx SVE copy integer immediate (predicated)
10x UNALLOCATED
110 FCPY
111 UNALLOCATED

SVE copy integer immediate (predicated)

These instructions are under SVE Integer Wide Immediate - Predicated.

313029282726252423222120191817161514131211109876543210
00000101size01Pg0Mshimm8Zd
Decode fields Instruction Details
M
0 CPY (immediate, zeroing)
1 CPY (immediate, merging)

SVE Permute Vector - One Source Quadwords

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
00000101op01op1001001
Decode fieldsInstruction detailsFeature
op0op1
00 DUPQFEAT_SVE2p1
01 0 EXTQFEAT_SVE2p1
01 1 UNALLOCATED-
1x UNALLOCATED-

SVE table lookup (three sources)

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
00000101size1Zm00101opZnZd
Decode fields Instruction Details
op
0 TBL
1 TBX

SVE Permute Vector - Unpredicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
000001011op0op1001110op2op3
Decode fieldsInstruction details
op0op1op2op3
00 000 DUP (scalar)
00 100 INSR (scalar)
00 x10 UNALLOCATED
00 xx1 UNALLOCATED
01 xx0 0 SVE move predicate from vector
01 xx0 1 UNALLOCATED
01 xx1 0 SVE move predicate into vector
01 xx1 1 UNALLOCATED
10 0xx SVE unpack vector elements
10 100 INSR (SIMD&FP scalar)
10 110 UNALLOCATED
10 1x1 UNALLOCATED
11 000 REV (vector)
11 != 000 UNALLOCATED

SVE move predicate from vector

These instructions are under SVE Permute Vector - Unpredicated.

313029282726252423222120191817161514131211109876543210
00000101opc101opc20001110Zn0Pd
Decode fields Instruction Details Feature
opc opc2
00 00 UNALLOCATED-
00 01 PMOV (to predicate)byteFEAT_SVE2p1
00 1x PMOV (to predicate)halfwordFEAT_SVE2p1
01 PMOV (to predicate)wordFEAT_SVE2p1
1x PMOV (to predicate)doublewordFEAT_SVE2p1

SVE move predicate into vector

These instructions are under SVE Permute Vector - Unpredicated.

313029282726252423222120191817161514131211109876543210
00000101opc101opc210011100PnZd
Decode fields Instruction Details Feature
opc opc2
00 00 UNALLOCATED-
00 01 PMOV (to vector)byteFEAT_SVE2p1
00 1x PMOV (to vector)halfwordFEAT_SVE2p1
01 PMOV (to vector)wordFEAT_SVE2p1
1x PMOV (to vector)doublewordFEAT_SVE2p1

SVE unpack vector elements

These instructions are under SVE Permute Vector - Unpredicated.

313029282726252423222120191817161514131211109876543210
00000101size1100UH001110ZnZd
Decode fields Instruction Details
U H
0 0 SUNPKHI, SUNPKLOSUNPKLO
0 1 SUNPKHI, SUNPKLOSUNPKHI
1 0 UUNPKHI, UUNPKLOUUNPKLO
1 1 UUNPKHI, UUNPKLOUUNPKHI

SVE Permute Predicate

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
00000101op01op1010op2op3
Decode fieldsInstruction details
op0op1op2op3
00 1000x 0000 0 SVE unpack predicate elements
01 1000x 0000 0 UNALLOCATED
10 1000x 0000 0 UNALLOCATED
11 1000x 0000 0 UNALLOCATED
0xxxx xxx0 0 SVE permute predicate elements
0xxxx xxx1 0 UNALLOCATED
10100 0000 0 REV (predicate)
10101 0000 0 UNALLOCATED
10x0x 1000 0 UNALLOCATED
10x0x x100 0 UNALLOCATED
10x0x xx10 0 UNALLOCATED
10x0x xxx1 0 UNALLOCATED
10x1x 0 UNALLOCATED
11xxx 0 UNALLOCATED
1 UNALLOCATED

SVE unpack predicate elements

These instructions are under SVE Permute Predicate.

313029282726252423222120191817161514131211109876543210
000001010011000H0100000Pn0Pd
Decode fields Instruction Details
H
0 PUNPKHI, PUNPKLOPUNPKLO
1 PUNPKHI, PUNPKLOPUNPKHI

SVE permute predicate elements

These instructions are under SVE Permute Predicate.

313029282726252423222120191817161514131211109876543210
00000101size10Pm010opcH0Pn0Pd
Decode fields Instruction Details
opc H
00 0 ZIP1, ZIP2 (predicates)ZIP1
00 1 ZIP1, ZIP2 (predicates)ZIP2
01 0 UZP1, UZP2 (predicates)UZP1
01 1 UZP1, UZP2 (predicates)UZP2
10 0 TRN1, TRN2 (predicates)TRN1
10 1 TRN1, TRN2 (predicates)TRN2
11 UNALLOCATED

SVE permute vector elements

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
00000101size1Zm011opcZnZd
Decode fields Instruction Details
opc
000 ZIP1, ZIP2 (vectors)ZIP1
001 ZIP1, ZIP2 (vectors)ZIP2
010 UZP1, UZP2 (vectors)UZP1
011 UZP1, UZP2 (vectors)UZP2
100 TRN1, TRN2 (vectors)TRN1
101 TRN1, TRN2 (vectors)TRN2
11x UNALLOCATED

SVE Permute Vector - Predicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
000001011op0op1op210op3
Decode fieldsInstruction details
op0op1op2op3
0 000 0 0 CPY (SIMD&FP scalar)
0 000 1 0 COMPACT
0 000 1 SVE extract element to general register
0 001 0 SVE extract element to SIMD&FP scalar register
0 01x 0 SVE reverse within elements
0 01x 1 UNALLOCATED
0 100 0 1 CPY (scalar)
0 100 1 1 UNALLOCATED
0 100 0 SVE conditionally broadcast element to vector
0 101 0 SVE conditionally extract element to SIMD&FP scalar
0 110 0 0 SPLICEDestructive
0 110 1 0 SPLICEConstructive
0 110 1 UNALLOCATED
0 111 0 0 SVE reverse doublewords
0 111 0 1 UNALLOCATED
0 111 1 UNALLOCATED
0 x01 1 UNALLOCATED
1 000 0 UNALLOCATED
1 000 1 SVE conditionally extract element to general register
1 != 000 UNALLOCATED

SVE extract element to general register

These instructions are under SVE Permute Vector - Predicated.

313029282726252423222120191817161514131211109876543210
00000101size10000B101PgZnRd
Decode fields Instruction Details
B
0 LASTA (scalar)
1 LASTB (scalar)

SVE extract element to SIMD&FP scalar register

These instructions are under SVE Permute Vector - Predicated.

313029282726252423222120191817161514131211109876543210
00000101size10001B100PgZnVd
Decode fields Instruction Details
B
0 LASTA (SIMD&FP scalar)
1 LASTB (SIMD&FP scalar)

SVE reverse within elements

These instructions are under SVE Permute Vector - Predicated.

313029282726252423222120191817161514131211109876543210
00000101size1001opc100PgZnZd
Decode fields Instruction Details
opc
00 REVB, REVH, REVWREVB
01 REVB, REVH, REVWREVH
10 REVB, REVH, REVWREVW
11 RBIT

SVE conditionally broadcast element to vector

These instructions are under SVE Permute Vector - Predicated.

313029282726252423222120191817161514131211109876543210
00000101size10100B100PgZmZdn
Decode fields Instruction Details
B
0 CLASTA (vectors)
1 CLASTB (vectors)

SVE conditionally extract element to SIMD&FP scalar

These instructions are under SVE Permute Vector - Predicated.

313029282726252423222120191817161514131211109876543210
00000101size10101B100PgZmVdn
Decode fields Instruction Details
B
0 CLASTA (SIMD&FP scalar)
1 CLASTB (SIMD&FP scalar)

SVE reverse doublewords

These instructions are under SVE Permute Vector - Predicated.

313029282726252423222120191817161514131211109876543210
00000101size101110100PgZnZd
Decode fields Instruction Details Feature
size
00 REVDFEAT_SVE2p1
01 UNALLOCATED-
1x UNALLOCATED-

SVE conditionally extract element to general register

These instructions are under SVE Permute Vector - Predicated.

313029282726252423222120191817161514131211109876543210
00000101size11000B101PgZmRdn
Decode fields Instruction Details
B
0 CLASTA (scalar)
1 CLASTB (scalar)

SVE Permute Vector - Extract

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
000001010op01000
Decode fieldsInstruction details
op0
0 EXTDestructive
1 EXTConstructive

SVE Permute Vector - Segments

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
000001011op01000
Decode fieldsInstruction details
op0
0 SVE permute vector segments
1 UNALLOCATED

SVE permute vector segments

These instructions are under SVE Permute Vector - Segments.

313029282726252423222120191817161514131211109876543210
00000101101Zm000opcHZnZd
Decode fields Instruction Details Feature
opc H
00 0 ZIP1, ZIP2 (vectors)ZIP1FEAT_F64MM
00 1 ZIP1, ZIP2 (vectors)ZIP2FEAT_F64MM
01 0 UZP1, UZP2 (vectors)UZP1FEAT_F64MM
01 1 UZP1, UZP2 (vectors)UZP2FEAT_F64MM
10 UNALLOCATED-
11 0 TRN1, TRN2 (vectors)TRN1FEAT_F64MM
11 1 TRN1, TRN2 (vectors)TRN2FEAT_F64MM

SVE Integer Compare - Vectors

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
001001000op0
Decode fieldsInstruction details
op0
0 SVE integer compare vectors
1 SVE integer compare with wide elements

SVE integer compare vectors

These instructions are under SVE Integer Compare - Vectors.

313029282726252423222120191817161514131211109876543210
00100100size0Zmop0o2PgZnnePd
Decode fields Instruction Details
op o2 ne
0 0 0 CMP<cc> (vectors)CMPHS
0 0 1 CMP<cc> (vectors)CMPHI
0 1 0 CMP<cc> (wide elements)CMPEQ
0 1 1 CMP<cc> (wide elements)CMPNE
1 0 0 CMP<cc> (vectors)CMPGE
1 0 1 CMP<cc> (vectors)CMPGT
1 1 0 CMP<cc> (vectors)CMPEQ
1 1 1 CMP<cc> (vectors)CMPNE

SVE integer compare with wide elements

These instructions are under SVE Integer Compare - Vectors.

313029282726252423222120191817161514131211109876543210
00100100size0ZmU1ltPgZnnePd
Decode fields Instruction Details
U lt ne
0 0 0 CMP<cc> (wide elements)CMPGE
0 0 1 CMP<cc> (wide elements)CMPGT
0 1 0 CMP<cc> (wide elements)CMPLT
0 1 1 CMP<cc> (wide elements)CMPLE
1 0 0 CMP<cc> (wide elements)CMPHS
1 0 1 CMP<cc> (wide elements)CMPHI
1 1 0 CMP<cc> (wide elements)CMPLO
1 1 1 CMP<cc> (wide elements)CMPLS

SVE integer compare with unsigned immediate

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
00100100size1imm7ltPgZnnePd
Decode fields Instruction Details
lt ne
0 0 CMP<cc> (immediate)CMPHS
0 1 CMP<cc> (immediate)CMPHI
1 0 CMP<cc> (immediate)CMPLO
1 1 CMP<cc> (immediate)CMPLS

SVE integer compare with signed immediate

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
00100101size0imm5op0o2PgZnnePd
Decode fields Instruction Details
op o2 ne
0 0 0 CMP<cc> (immediate)CMPGE
0 0 1 CMP<cc> (immediate)CMPGT
0 1 0 CMP<cc> (immediate)CMPLT
0 1 1 CMP<cc> (immediate)CMPLE
1 0 0 CMP<cc> (immediate)CMPEQ
1 0 1 CMP<cc> (immediate)CMPNE
1 1 UNALLOCATED

SVE predicate logical operations

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
00100101opS00Pm01Pgo2Pno3Pd
Decode fields Instruction Details
op S o2 o3
0 0 0 0 AND (predicates)
0 0 0 1 BIC (predicates)
0 0 1 0 EOR (predicates)
0 0 1 1 SEL (predicates)
0 1 0 0 ANDS
0 1 0 1 BICS
0 1 1 0 EORS
0 1 1 1 UNALLOCATED
1 0 0 0 ORR (predicates)
1 0 0 1 ORN (predicates)
1 0 1 0 NOR
1 0 1 1 NAND
1 1 0 0 ORRS
1 1 0 1 ORNS
1 1 1 0 NORS
1 1 1 1 NANDS

SVE Propagate Break

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
001001010011op0
Decode fieldsInstruction details
op0
0 SVE propagate break from previous partition
1 UNALLOCATED

SVE propagate break from previous partition

These instructions are under SVE Propagate Break.

313029282726252423222120191817161514131211109876543210
00100101opS00Pm11Pg0PnBPd
Decode fields Instruction Details
op S B
0 0 0 BRKPA
0 0 1 BRKPB
0 1 0 BRKPAS
0 1 1 BRKPBS
1 UNALLOCATED

SVE Partition Break

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
00100101op001op101op2op3
Decode fieldsInstruction details
op0op1op2op3
0 1000 0 0 SVE propagate break to next partition
0 1000 0 1 UNALLOCATED
0 x000 1 UNALLOCATED
0 x1xx UNALLOCATED
0 xx1x UNALLOCATED
0 xxx1 UNALLOCATED
1 0000 1 UNALLOCATED
1 != 0000 UNALLOCATED
0000 0 SVE partition break condition

SVE propagate break to next partition

These instructions are under SVE Partition Break.

313029282726252423222120191817161514131211109876543210
001001010S01100001Pg0Pn0Pdm
Decode fields Instruction Details
S
0 BRKN
1 BRKNS

SVE partition break condition

These instructions are under SVE Partition Break.

313029282726252423222120191817161514131211109876543210
00100101BS01000001Pg0PnMPd
Decode fields Instruction Details
B S M
1 1 UNALLOCATED
0 0 BRKA
0 1 0 BRKAS
1 0 BRKB
1 1 0 BRKBS

SVE Predicate Misc

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
0010010101op011op1op2op3op4
Decode fieldsInstruction details
op0op1op2op3op4
0000 x0 0 SVE predicate test
0100 x0 0 UNALLOCATED
0x10 x0 0 UNALLOCATED
0xx1 x0 0 UNALLOCATED
0xxx x1 0 UNALLOCATED
1000 000 00 0 SVE predicate first active
1000 000 != 00 0 UNALLOCATED
1000 100 10 0000 0 SVE predicate zero
1000 100 10 != 0000 0 UNALLOCATED
1000 110 00 0 SVE predicate read from FFR (predicated)
1001 000 0x 0 UNALLOCATED
1001 000 10 0 PNEXT
1001 000 11 0 UNALLOCATED
1001 100 10 0 UNALLOCATED
1001 110 00 0000 0 SVE predicate read from FFR (unpredicated)
1001 110 00 != 0000 0 UNALLOCATED
100x 010 0 UNALLOCATED
100x 100 0x 0 SVE predicate initialize
100x 100 11 0 UNALLOCATED
100x 110 != 00 0 UNALLOCATED
100x xx1 0 UNALLOCATED
110x 0 UNALLOCATED
1x1x 0 UNALLOCATED
1 UNALLOCATED

SVE predicate test

These instructions are under SVE Predicate Misc.

313029282726252423222120191817161514131211109876543210
00100101opS01000011Pg0Pn0opc2
Decode fields Instruction Details
op S opc2
0 0 UNALLOCATED
0 1 0000 PTEST
0 1 0001 UNALLOCATED
0 1 001x UNALLOCATED
0 1 01xx UNALLOCATED
0 1 1xxx UNALLOCATED
1 UNALLOCATED

SVE predicate first active

These instructions are under SVE Predicate Misc.

313029282726252423222120191817161514131211109876543210
00100101opS0110001100000Pg0Pdn
Decode fields Instruction Details
op S
0 0 UNALLOCATED
0 1 PFIRST
1 UNALLOCATED

SVE predicate zero

These instructions are under SVE Predicate Misc.

313029282726252423222120191817161514131211109876543210
00100101opS011000111001000000Pd
Decode fields Instruction Details
op S
0 0 PFALSE
0 1 UNALLOCATED
1 UNALLOCATED

SVE predicate read from FFR (predicated)

These instructions are under SVE Predicate Misc.

313029282726252423222120191817161514131211109876543210
00100101opS0110001111000Pg0Pd
Decode fields Instruction Details
op S
0 0 RDFFR (predicated)
0 1 RDFFRS
1 UNALLOCATED

SVE predicate read from FFR (unpredicated)

These instructions are under SVE Predicate Misc.

313029282726252423222120191817161514131211109876543210
00100101opS011001111100000000Pd
Decode fields Instruction Details
op S
0 0 RDFFR (unpredicated)
0 1 UNALLOCATED
1 UNALLOCATED

SVE predicate initialize

These instructions are under SVE Predicate Misc.

313029282726252423222120191817161514131211109876543210
00100101size01100S111000pattern0Pd
Decode fields Instruction Details
S
0 PTRUE (predicate)
1 PTRUES

SVE Integer Compare - Scalars

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
00100101100op0op1op2
Decode fieldsInstruction details
op0op1op2
0x SVE integer compare scalar count and limit
10 00 0000 SVE conditionally terminate scalars
10 00 != 0000 UNALLOCATED
11 00 SVE pointer conflict compare
1x != 00 UNALLOCATED

SVE integer compare scalar count and limit

These instructions are under SVE Integer Compare - Scalars.

313029282726252423222120191817161514131211109876543210
00100101size1Rm000sfUltRneqPd
Decode fields Instruction Details
U lt eq
0 0 0 WHILEGE (predicate)
0 0 1 WHILEGT (predicate)
0 1 0 WHILELT (predicate)
0 1 1 WHILELE (predicate)
1 0 0 WHILEHS (predicate)
1 0 1 WHILEHI (predicate)
1 1 0 WHILELO (predicate)
1 1 1 WHILELS (predicate)

SVE conditionally terminate scalars

These instructions are under SVE Integer Compare - Scalars.

313029282726252423222120191817161514131211109876543210
00100101opsz1Rm001000Rnne0000
Decode fields Instruction Details
op ne
0 UNALLOCATED
1 0 CTERMEQ, CTERMNECTERMEQ
1 1 CTERMEQ, CTERMNECTERMNE

SVE pointer conflict compare

These instructions are under SVE Integer Compare - Scalars.

313029282726252423222120191817161514131211109876543210
00100101size1Rm001100RnrwPd
Decode fields Instruction Details
rw
0 WHILEWR
1 WHILERW

SVE broadcast predicate element

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
00100101i1tszh1tszlRv01PnSPm0Pd
Decode fields Instruction Details Feature
S
0 PSELFEAT_SVE2p1
1 UNALLOCATED-

SVE Scalar Integer Compare - Predicate-as-counter

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
001001011op001op1op21op3
Decode fieldsInstruction detailsFeature
op0op1op2op3
00000 110 SVE extract mask predicate from predicate-as-counter-
00000 111 000000 0 PTRUE (predicate as counter)FEAT_SVE2p1
00000 111 000000 1 UNALLOCATED-
00000 111 != 000000 UNALLOCATED-
!= 00000 11x UNALLOCATED-
01x SVE integer compare scalar count and limit (predicate pair)-
x0x SVE integer compare scalar count and limit (predicate-as-counter)-

SVE extract mask predicate from predicate-as-counter

These instructions are under SVE Scalar Integer Compare - Predicate-as-counter.

313029282726252423222120191817161514131211109876543210
00100101size10000001110opcPNn1Pd
Decode fields Instruction Details Feature
opc
0xx PEXT (predicate)FEAT_SVE2p1
10x PEXT (predicate pair)FEAT_SVE2p1
11x UNALLOCATED-

SVE integer compare scalar count and limit (predicate pair)

These instructions are under SVE Scalar Integer Compare - Predicate-as-counter.

313029282726252423222120191817161514131211109876543210
00100101size1Rm0101UltRn1Pdeq
Decode fields Instruction Details Feature
U lt eq
0 0 0 WHILEGE (predicate pair)FEAT_SVE2p1
0 0 1 WHILEGT (predicate pair)FEAT_SVE2p1
0 1 0 WHILELT (predicate pair)FEAT_SVE2p1
0 1 1 WHILELE (predicate pair)FEAT_SVE2p1
1 0 0 WHILEHS (predicate pair)FEAT_SVE2p1
1 0 1 WHILEHI (predicate pair)FEAT_SVE2p1
1 1 0 WHILELO (predicate pair)FEAT_SVE2p1
1 1 1 WHILELS (predicate pair)FEAT_SVE2p1

SVE integer compare scalar count and limit (predicate-as-counter)

These instructions are under SVE Scalar Integer Compare - Predicate-as-counter.

313029282726252423222120191817161514131211109876543210
00100101size1Rm01vl0UltRn1eqPNd
Decode fields Instruction Details Feature
U lt eq
0 0 0 WHILEGE (predicate as counter)FEAT_SVE2p1
0 0 1 WHILEGT (predicate as counter)FEAT_SVE2p1
0 1 0 WHILELT (predicate as counter)FEAT_SVE2p1
0 1 1 WHILELE (predicate as counter)FEAT_SVE2p1
1 0 0 WHILEHS (predicate as counter)FEAT_SVE2p1
1 0 1 WHILEHI (predicate as counter)FEAT_SVE2p1
1 1 0 WHILELO (predicate as counter)FEAT_SVE2p1
1 1 1 WHILELS (predicate as counter)FEAT_SVE2p1

SVE Integer Wide Immediate - Unpredicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
001001011op0op111
Decode fieldsInstruction details
op0op1
00 SVE integer add/subtract immediate (unpredicated)
01 SVE integer min/max immediate (unpredicated)
10 SVE integer multiply immediate (unpredicated)
11 0 SVE broadcast integer immediate (unpredicated)
11 1 SVE broadcast floating-point immediate (unpredicated)

SVE integer add/subtract immediate (unpredicated)

These instructions are under SVE Integer Wide Immediate - Unpredicated.

313029282726252423222120191817161514131211109876543210
00100101size100opc11shimm8Zdn
Decode fields Instruction Details
opc
000 ADD (immediate)
001 SUB (immediate)
010 UNALLOCATED
011 SUBR (immediate)
100 SQADD (immediate)
101 UQADD (immediate)
110 SQSUB (immediate)
111 UQSUB (immediate)

SVE integer min/max immediate (unpredicated)

These instructions are under SVE Integer Wide Immediate - Unpredicated.

313029282726252423222120191817161514131211109876543210
00100101size101opc11o2imm8Zdn
Decode fields Instruction Details
opc o2
0xx 1 UNALLOCATED
000 0 SMAX (immediate)
001 0 UMAX (immediate)
010 0 SMIN (immediate)
011 0 UMIN (immediate)
1xx UNALLOCATED

SVE integer multiply immediate (unpredicated)

These instructions are under SVE Integer Wide Immediate - Unpredicated.

313029282726252423222120191817161514131211109876543210
00100101size110opc11o2imm8Zdn
Decode fields Instruction Details
opc o2
000 0 MUL (immediate)
000 1 UNALLOCATED
001 UNALLOCATED
01x UNALLOCATED
1xx UNALLOCATED

SVE broadcast integer immediate (unpredicated)

These instructions are under SVE Integer Wide Immediate - Unpredicated.

313029282726252423222120191817161514131211109876543210
00100101size111opc011shimm8Zd
Decode fields Instruction Details
opc
00 DUP (immediate)
01 UNALLOCATED
1x UNALLOCATED

SVE broadcast floating-point immediate (unpredicated)

These instructions are under SVE Integer Wide Immediate - Unpredicated.

313029282726252423222120191817161514131211109876543210
00100101size111opc111o2imm8Zd
Decode fields Instruction Details
opc o2
00 0 FDUP
00 1 UNALLOCATED
01 UNALLOCATED
1x UNALLOCATED

SVE Predicate Count

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
0010010110010op0op1
Decode fieldsInstruction details
op0op1
000 1 SVE predicate count (predicate-as-counter)
!= 000 1 UNALLOCATED
0 SVE predicate count

SVE predicate count (predicate-as-counter)

These instructions are under SVE Predicate Count.

313029282726252423222120191817161514131211109876543210
00100101size100opc10000vl1PNnRd
Decode fields Instruction Details Feature
opc
000 CNTP (predicate as counter)FEAT_SVE2p1
001 UNALLOCATED-
01x UNALLOCATED-
1xx UNALLOCATED-

SVE predicate count

These instructions are under SVE Predicate Count.

313029282726252423222120191817161514131211109876543210
00100101size100opc10Pg0PnRd
Decode fields Instruction Details
opc
000 CNTP (predicate)
001 UNALLOCATED
01x UNALLOCATED
1xx UNALLOCATED

SVE Inc/Dec by Predicate Count

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
00100101101op01000op1
Decode fieldsInstruction details
op0op1
0 0 SVE saturating inc/dec vector by predicate count
0 1 SVE saturating inc/dec register by predicate count
1 0 SVE inc/dec vector by predicate count
1 1 SVE inc/dec register by predicate count

SVE saturating inc/dec vector by predicate count

These instructions are under SVE Inc/Dec by Predicate Count.

313029282726252423222120191817161514131211109876543210
00100101size1010DU10000opcPmZdn
Decode fields Instruction Details
D U opc
01 UNALLOCATED
1x UNALLOCATED
0 0 00 SQINCP (vector)
0 1 00 UQINCP (vector)
1 0 00 SQDECP (vector)
1 1 00 UQDECP (vector)

SVE saturating inc/dec register by predicate count

These instructions are under SVE Inc/Dec by Predicate Count.

313029282726252423222120191817161514131211109876543210
00100101size1010DU10001sfopPmRdn
Decode fields Instruction Details
D U sf op
1 UNALLOCATED
0 0 0 0 SQINCP (scalar)32-bit
0 0 1 0 SQINCP (scalar)64-bit
0 1 0 0 UQINCP (scalar)32-bit
0 1 1 0 UQINCP (scalar)64-bit
1 0 0 0 SQDECP (scalar)32-bit
1 0 1 0 SQDECP (scalar)64-bit
1 1 0 0 UQDECP (scalar)32-bit
1 1 1 0 UQDECP (scalar)64-bit

SVE inc/dec vector by predicate count

These instructions are under SVE Inc/Dec by Predicate Count.

313029282726252423222120191817161514131211109876543210
00100101size1011opD10000opc2PmZdn
Decode fields Instruction Details
op D opc2
0 01 UNALLOCATED
0 1x UNALLOCATED
0 0 00 INCP (vector)
0 1 00 DECP (vector)
1 UNALLOCATED

SVE inc/dec register by predicate count

These instructions are under SVE Inc/Dec by Predicate Count.

313029282726252423222120191817161514131211109876543210
00100101size1011opD10001opc2PmRdn
Decode fields Instruction Details
op D opc2
0 01 UNALLOCATED
0 1x UNALLOCATED
0 0 00 INCP (scalar)
0 1 00 DECP (scalar)
1 UNALLOCATED

SVE Write FFR

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
00100101101op0op11001op2op3op4
Decode fieldsInstruction details
op0op1op2op3op4
0 00 000 00000 SVE FFR write from predicate
1 00 000 0000 00000 SVE FFR initialise
1 00 000 1xxx 00000 UNALLOCATED
1 00 000 x1xx 00000 UNALLOCATED
1 00 000 xx1x 00000 UNALLOCATED
1 00 000 xxx1 00000 UNALLOCATED
00 000 != 00000 UNALLOCATED
00 != 000 UNALLOCATED
!= 00 UNALLOCATED

SVE FFR write from predicate

These instructions are under SVE Write FFR.

313029282726252423222120191817161514131211109876543210
00100101opc1010001001000Pn00000
Decode fields Instruction Details
opc
00 WRFFR
01 UNALLOCATED
1x UNALLOCATED

SVE FFR initialise

These instructions are under SVE Write FFR.

313029282726252423222120191817161514131211109876543210
00100101opc1011001001000000000000
Decode fields Instruction Details
opc
00 SETFFR
01 UNALLOCATED
1x UNALLOCATED

SVE Integer Multiply-Add - Unpredicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
0100010000op0
Decode fieldsInstruction details
op0
0000x SVE integer dot product (unpredicated)
0001x SVE2 saturating multiply-add interleaved long
001xx CDOT (vectors)
01xxx SVE2 complex integer multiply-add
10xxx SVE2 integer multiply-add long
110xx SVE2 saturating multiply-add long
1110x SVE2 saturating multiply-add high
11110 SVE mixed sign dot product
11111 UNALLOCATED

SVE integer dot product (unpredicated)

These instructions are under SVE Integer Multiply-Add - Unpredicated.

313029282726252423222120191817161514131211109876543210
01000100size0Zm00000UZnZda
Decode fields Instruction Details
U
0 SDOT (4-way, vectors)
1 UDOT (4-way, vectors)

SVE2 saturating multiply-add interleaved long

These instructions are under SVE Integer Multiply-Add - Unpredicated.

313029282726252423222120191817161514131211109876543210
01000100size0Zm00001SZnZda
Decode fields Instruction Details
S
0 SQDMLALBT
1 SQDMLSLBT

SVE2 complex integer multiply-add

These instructions are under SVE Integer Multiply-Add - Unpredicated.

313029282726252423222120191817161514131211109876543210
01000100size0Zm001oprotZnZda
Decode fields Instruction Details
op
0 CMLA (vectors)
1 SQRDCMLAH (vectors)

SVE2 integer multiply-add long

These instructions are under SVE Integer Multiply-Add - Unpredicated.

313029282726252423222120191817161514131211109876543210
01000100size0Zm010SUTZnZda
Decode fields Instruction Details
S U T
0 0 0 SMLALB (vectors)
0 0 1 SMLALT (vectors)
0 1 0 UMLALB (vectors)
0 1 1 UMLALT (vectors)
1 0 0 SMLSLB (vectors)
1 0 1 SMLSLT (vectors)
1 1 0 UMLSLB (vectors)
1 1 1 UMLSLT (vectors)

SVE2 saturating multiply-add long

These instructions are under SVE Integer Multiply-Add - Unpredicated.

313029282726252423222120191817161514131211109876543210
01000100size0Zm0110STZnZda
Decode fields Instruction Details
S T
0 0 SQDMLALB (vectors)
0 1 SQDMLALT (vectors)
1 0 SQDMLSLB (vectors)
1 1 SQDMLSLT (vectors)

SVE2 saturating multiply-add high

These instructions are under SVE Integer Multiply-Add - Unpredicated.

313029282726252423222120191817161514131211109876543210
01000100size0Zm01110SZnZda
Decode fields Instruction Details
S
0 SQRDMLAH (vectors)
1 SQRDMLSH (vectors)

SVE mixed sign dot product

These instructions are under SVE Integer Multiply-Add - Unpredicated.

313029282726252423222120191817161514131211109876543210
01000100size0Zm011110ZnZda
Decode fields Instruction Details Feature
size
0x UNALLOCATED-
10 USDOT (vectors)FEAT_I8MM
11 UNALLOCATED-

SVE2 Integer - Predicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
010001000op010op1
Decode fieldsInstruction details
op0op1
0010 1 SVE2 integer pairwise add and accumulate long
0011 1 UNALLOCATED
011x 1 UNALLOCATED
0x0x 1 SVE2 integer unary operations (predicated)
0xxx 0 SVE2 saturating/rounding bitwise shift left (predicated)
10xx 0 SVE2 integer halving add/subtract (predicated)
10xx 1 SVE2 integer pairwise arithmetic
11xx 0 SVE2 saturating add/subtract
11xx 1 UNALLOCATED

SVE2 integer pairwise add and accumulate long

These instructions are under SVE2 Integer - Predicated.

313029282726252423222120191817161514131211109876543210
01000100size00010U101PgZnZda
Decode fields Instruction Details
U
0 SADALP
1 UADALP

SVE2 integer unary operations (predicated)

These instructions are under SVE2 Integer - Predicated.

313029282726252423222120191817161514131211109876543210
01000100size00Q0opc101PgZnZd
Decode fields Instruction Details
Q opc
1x UNALLOCATED
0 00 URECPE
0 01 URSQRTE
1 00 SQABS
1 01 SQNEG

SVE2 saturating/rounding bitwise shift left (predicated)

These instructions are under SVE2 Integer - Predicated.

313029282726252423222120191817161514131211109876543210
01000100size00QRNU100PgZmZdn
Decode fields Instruction Details
Q R N U
0 0 UNALLOCATED
0 0 1 0 SRSHL
0 0 1 1 URSHL
0 1 1 0 SRSHLR
0 1 1 1 URSHLR
1 0 0 0 SQSHL (vectors)
1 0 0 1 UQSHL (vectors)
1 0 1 0 SQRSHL
1 0 1 1 UQRSHL
1 1 0 0 SQSHLR
1 1 0 1 UQSHLR
1 1 1 0 SQRSHLR
1 1 1 1 UQRSHLR

SVE2 integer halving add/subtract (predicated)

These instructions are under SVE2 Integer - Predicated.

313029282726252423222120191817161514131211109876543210
01000100size010RSU100PgZmZdn
Decode fields Instruction Details
R S U
0 0 0 SHADD
0 0 1 UHADD
0 1 0 SHSUB
0 1 1 UHSUB
1 0 0 SRHADD
1 0 1 URHADD
1 1 0 SHSUBR
1 1 1 UHSUBR

SVE2 integer pairwise arithmetic

These instructions are under SVE2 Integer - Predicated.

313029282726252423222120191817161514131211109876543210
01000100size010opcU101PgZmZdn
Decode fields Instruction Details
opc U
00 0 UNALLOCATED
00 1 ADDP
01 UNALLOCATED
10 0 SMAXP
10 1 UMAXP
11 0 SMINP
11 1 UMINP

SVE2 saturating add/subtract

These instructions are under SVE2 Integer - Predicated.

313029282726252423222120191817161514131211109876543210
01000100size011opSU100PgZmZdn
Decode fields Instruction Details
op S U
0 0 0 SQADD (vectors, predicated)
0 0 1 UQADD (vectors, predicated)
0 1 0 SQSUB (vectors, predicated)
0 1 1 UQSUB (vectors, predicated)
1 0 0 SUQADD
1 0 1 USQADD
1 1 0 SQSUBR
1 1 1 UQSUBR

SVE integer clamp

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01000100size0Zm11000UZnZd
Decode fields Instruction Details Feature
U
0 SCLAMPFEAT_SVE2p1
1 UCLAMPFEAT_SVE2p1

SVE2 multiply-add (checked pointer)

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01000100opc0Zm1101opc2ZnZda
Decode fields Instruction Details Feature
opc opc2
0x UNALLOCATED-
10 UNALLOCATED-
11 x1 UNALLOCATED-
11 00 MLAPTFEAT_CPA
11 10 MADPTFEAT_CPA

SVE permute vector elements (quadwords)

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01000100size0Zm111opcZnZd
Decode fields Instruction Details Feature
opc
000 ZIPQ1FEAT_SVE2p1
001 ZIPQ2FEAT_SVE2p1
010 UZPQ1FEAT_SVE2p1
011 UZPQ2FEAT_SVE2p1
10x UNALLOCATED-
110 TBLQFEAT_SVE2p1
111 UNALLOCATED-

SVE Multiply - Indexed

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
010001001op0
Decode fieldsInstruction details
op0
00000x SVE integer dot product (indexed)
00001x SVE2 integer multiply-add (indexed)
00010x SVE2 saturating multiply-add high (indexed)
00011x SVE mixed sign dot product (indexed)
001xxx SVE2 saturating multiply-add (indexed)
0100xx SVE2 complex integer dot product (indexed)
0101xx UNALLOCATED
0110xx SVE2 complex integer multiply-add (indexed)
0111xx SVE2 complex saturating multiply-add (indexed)
10xxxx SVE2 integer multiply-add long (indexed)
110xxx SVE2 integer multiply long (indexed)
1110xx SVE2 saturating multiply (indexed)
11110x SVE2 saturating multiply high (indexed)
111110 SVE2 integer multiply (indexed)
111111 UNALLOCATED

SVE integer dot product (indexed)

These instructions are under SVE Multiply - Indexed.

313029282726252423222120191817161514131211109876543210
01000100size1opc00000UZnZda
Decode fields Instruction Details
size U
0x UNALLOCATED
10 0 SDOT (4-way, indexed)32-bit
10 1 UDOT (4-way, indexed)32-bit
11 0 SDOT (4-way, indexed)64-bit
11 1 UDOT (4-way, indexed)64-bit

SVE2 integer multiply-add (indexed)

These instructions are under SVE Multiply - Indexed.

313029282726252423222120191817161514131211109876543210
01000100size1opc00001SZnZda
Decode fields Instruction Details
size S
0x 0 MLA (indexed)16-bit
0x 1 MLS (indexed)16-bit
10 0 MLA (indexed)32-bit
10 1 MLS (indexed)32-bit
11 0 MLA (indexed)64-bit
11 1 MLS (indexed)64-bit

SVE2 saturating multiply-add high (indexed)

These instructions are under SVE Multiply - Indexed.

313029282726252423222120191817161514131211109876543210
01000100size1opc00010SZnZda
Decode fields Instruction Details
size S
0x 0 SQRDMLAH (indexed)16-bit
0x 1 SQRDMLSH (indexed)16-bit
10 0 SQRDMLAH (indexed)32-bit
10 1 SQRDMLSH (indexed)32-bit
11 0 SQRDMLAH (indexed)64-bit
11 1 SQRDMLSH (indexed)64-bit

SVE mixed sign dot product (indexed)

These instructions are under SVE Multiply - Indexed.

313029282726252423222120191817161514131211109876543210
01000100size1opc00011UZnZda
Decode fields Instruction Details Feature
size U
0x UNALLOCATED-
10 0 USDOT (indexed)FEAT_I8MM
10 1 SUDOTFEAT_I8MM
11 UNALLOCATED-

SVE2 saturating multiply-add (indexed)

These instructions are under SVE Multiply - Indexed.

313029282726252423222120191817161514131211109876543210
01000100size1opc001SilTZnZda
Decode fields Instruction Details
size S T
0x UNALLOCATED
10 0 0 SQDMLALB (indexed)32-bit
10 0 1 SQDMLALT (indexed)32-bit
10 1 0 SQDMLSLB (indexed)32-bit
10 1 1 SQDMLSLT (indexed)32-bit
11 0 0 SQDMLALB (indexed)64-bit
11 0 1 SQDMLALT (indexed)64-bit
11 1 0 SQDMLSLB (indexed)64-bit
11 1 1 SQDMLSLT (indexed)64-bit

SVE2 complex integer dot product (indexed)

These instructions are under SVE Multiply - Indexed.

313029282726252423222120191817161514131211109876543210
01000100size1opc0100rotZnZda
Decode fields Instruction Details
size
0x UNALLOCATED
10 CDOT (indexed)32-bit
11 CDOT (indexed)64-bit

SVE2 complex integer multiply-add (indexed)

These instructions are under SVE Multiply - Indexed.

313029282726252423222120191817161514131211109876543210
01000100size1opc0110rotZnZda
Decode fields Instruction Details
size
0x UNALLOCATED
10 CMLA (indexed)16-bit
11 CMLA (indexed)32-bit

SVE2 complex saturating multiply-add (indexed)

These instructions are under SVE Multiply - Indexed.

313029282726252423222120191817161514131211109876543210
01000100size1opc0111rotZnZda
Decode fields Instruction Details
size
0x UNALLOCATED
10 SQRDCMLAH (indexed)16-bit
11 SQRDCMLAH (indexed)32-bit

SVE2 integer multiply-add long (indexed)

These instructions are under SVE Multiply - Indexed.

313029282726252423222120191817161514131211109876543210
01000100size1opc10SUilTZnZda
Decode fields Instruction Details
size S U T
0x UNALLOCATED
10 0 0 0 SMLALB (indexed)32-bit
10 0 0 1 SMLALT (indexed)32-bit
10 0 1 0 UMLALB (indexed)32-bit
10 0 1 1 UMLALT (indexed)32-bit
10 1 0 0 SMLSLB (indexed)32-bit
10 1 0 1 SMLSLT (indexed)32-bit
10 1 1 0 UMLSLB (indexed)32-bit
10 1 1 1 UMLSLT (indexed)32-bit
11 0 0 0 SMLALB (indexed)64-bit
11 0 0 1 SMLALT (indexed)64-bit
11 0 1 0 UMLALB (indexed)64-bit
11 0 1 1 UMLALT (indexed)64-bit
11 1 0 0 SMLSLB (indexed)64-bit
11 1 0 1 SMLSLT (indexed)64-bit
11 1 1 0 UMLSLB (indexed)64-bit
11 1 1 1 UMLSLT (indexed)64-bit

SVE2 integer multiply long (indexed)

These instructions are under SVE Multiply - Indexed.

313029282726252423222120191817161514131211109876543210
01000100size1opc110UilTZnZd
Decode fields Instruction Details
size U T
0x UNALLOCATED
10 0 0 SMULLB (indexed)32-bit
10 0 1 SMULLT (indexed)32-bit
10 1 0 UMULLB (indexed)32-bit
10 1 1 UMULLT (indexed)32-bit
11 0 0 SMULLB (indexed)64-bit
11 0 1 SMULLT (indexed)64-bit
11 1 0 UMULLB (indexed)64-bit
11 1 1 UMULLT (indexed)64-bit

SVE2 saturating multiply (indexed)

These instructions are under SVE Multiply - Indexed.

313029282726252423222120191817161514131211109876543210
01000100size1opc1110ilTZnZd
Decode fields Instruction Details
size T
0x UNALLOCATED
10 0 SQDMULLB (indexed)32-bit
10 1 SQDMULLT (indexed)32-bit
11 0 SQDMULLB (indexed)64-bit
11 1 SQDMULLT (indexed)64-bit

SVE2 saturating multiply high (indexed)

These instructions are under SVE Multiply - Indexed.

313029282726252423222120191817161514131211109876543210
01000100size1opc11110RZnZd
Decode fields Instruction Details
size R
0x 0 SQDMULH (indexed)16-bit
0x 1 SQRDMULH (indexed)16-bit
10 0 SQDMULH (indexed)32-bit
10 1 SQRDMULH (indexed)32-bit
11 0 SQDMULH (indexed)64-bit
11 1 SQRDMULH (indexed)64-bit

SVE2 integer multiply (indexed)

These instructions are under SVE Multiply - Indexed.

313029282726252423222120191817161514131211109876543210
01000100size1opc111110ZnZd
Decode fields Instruction Details
size
0x MUL (indexed)16-bit
10 MUL (indexed)32-bit
11 MUL (indexed)64-bit

SVE two-way dot product

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01000100000Zm11001UZnZda
Decode fields Instruction Details Feature
U
0 SDOT (2-way, vectors)FEAT_SVE2p1
1 UDOT (2-way, vectors)FEAT_SVE2p1

SVE two-way dot product (indexed)

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01000100100opc11001UZnZda
Decode fields Instruction Details Feature
U
0 SDOT (2-way, indexed)FEAT_SVE2p1
1 UDOT (2-way, indexed)FEAT_SVE2p1

SVE2 Widening Integer Arithmetic

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
0100010100op0
Decode fieldsInstruction details
op0
0x SVE2 integer add/subtract long
10 SVE2 integer add/subtract wide
11 SVE2 integer multiply long

SVE2 integer add/subtract long

These instructions are under SVE2 Widening Integer Arithmetic.

313029282726252423222120191817161514131211109876543210
01000101size0Zm00opSUTZnZd
Decode fields Instruction Details
op S U T
0 0 0 0 SADDLB
0 0 0 1 SADDLT
0 0 1 0 UADDLB
0 0 1 1 UADDLT
0 1 0 0 SSUBLB
0 1 0 1 SSUBLT
0 1 1 0 USUBLB
0 1 1 1 USUBLT
1 0 UNALLOCATED
1 1 0 0 SABDLB
1 1 0 1 SABDLT
1 1 1 0 UABDLB
1 1 1 1 UABDLT

SVE2 integer add/subtract wide

These instructions are under SVE2 Widening Integer Arithmetic.

313029282726252423222120191817161514131211109876543210
01000101size0Zm010SUTZnZd
Decode fields Instruction Details
S U T
0 0 0 SADDWB
0 0 1 SADDWT
0 1 0 UADDWB
0 1 1 UADDWT
1 0 0 SSUBWB
1 0 1 SSUBWT
1 1 0 USUBWB
1 1 1 USUBWT

SVE2 integer multiply long

These instructions are under SVE2 Widening Integer Arithmetic.

313029282726252423222120191817161514131211109876543210
01000101size0Zm011opUTZnZd
Decode fields Instruction Details Feature
size op U T
0 0 0 SQDMULLB (vectors)-
0 0 1 SQDMULLT (vectors)-
1 0 0 SMULLB (vectors)-
1 0 1 SMULLT (vectors)-
1 1 0 UMULLB (vectors)-
1 1 1 UMULLT (vectors)-
!= 00 0 1 0 PMULLB16-bit or 64-bit elements-
!= 00 0 1 1 PMULLT16-bit or 64-bit elements-
00 0 1 0 PMULLB128-bit elementFEAT_SVE_PMULL128
00 0 1 1 PMULLT128-bit elementFEAT_SVE_PMULL128

SVE Misc

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01000101op0010op1
Decode fieldsInstruction details
op0op1
0 10xx SVE2 bitwise shift left long
1 10xx UNALLOCATED
00xx SVE2 integer add/subtract interleaved long
010x SVE2 bitwise exclusive-or interleaved
0110 SVE integer matrix multiply accumulate
0111 UNALLOCATED
11xx SVE2 bitwise permute

SVE2 bitwise shift left long

These instructions are under SVE Misc.

313029282726252423222120191817161514131211109876543210
010001010tszh0tszlimm31010UTZnZd
Decode fields Instruction Details
U T
0 0 SSHLLB
0 1 SSHLLT
1 0 USHLLB
1 1 USHLLT

SVE2 integer add/subtract interleaved long

These instructions are under SVE Misc.

313029282726252423222120191817161514131211109876543210
01000101size0Zm1000StbZnZd
Decode fields Instruction Details
S tb
0 0 SADDLBT
0 1 UNALLOCATED
1 0 SSUBLBT
1 1 SSUBLTB

SVE2 bitwise exclusive-or interleaved

These instructions are under SVE Misc.

313029282726252423222120191817161514131211109876543210
01000101size0Zm10010tbZnZd
Decode fields Instruction Details
tb
0 EORBT
1 EORTB

SVE integer matrix multiply accumulate

These instructions are under SVE Misc.

313029282726252423222120191817161514131211109876543210
01000101uns0Zm100110ZnZd
Decode fields Instruction Details Feature
uns
00 SMMLAFEAT_I8MM
01 UNALLOCATED-
10 USMMLAFEAT_I8MM
11 UMMLAFEAT_I8MM

SVE2 bitwise permute

These instructions are under SVE Misc.

313029282726252423222120191817161514131211109876543210
01000101size0Zm1011opcZnZd
Decode fields Instruction Details Feature
opc
00 BEXTFEAT_SVE_BitPerm
01 BDEPFEAT_SVE_BitPerm
10 BGRPFEAT_SVE_BitPerm
11 UNALLOCATED-

SVE2 Accumulate

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
010001010op011op1
Decode fieldsInstruction details
op0op1
0000 011 SVE2 complex integer add
!= 0000 011 UNALLOCATED
00x SVE2 integer absolute difference and accumulate long
010 SVE2 integer add/subtract long with carry
10x SVE2 bitwise shift right and accumulate
110 SVE2 bitwise shift and insert
111 SVE2 integer absolute difference and accumulate

SVE2 complex integer add

These instructions are under SVE2 Accumulate.

313029282726252423222120191817161514131211109876543210
01000101size00000op11011rotZmZdn
Decode fields Instruction Details
op
0 CADD
1 SQCADD

SVE2 integer absolute difference and accumulate long

These instructions are under SVE2 Accumulate.

313029282726252423222120191817161514131211109876543210
01000101size0Zm1100UTZnZda
Decode fields Instruction Details
U T
0 0 SABALB
0 1 SABALT
1 0 UABALB
1 1 UABALT

SVE2 integer add/subtract long with carry

These instructions are under SVE2 Accumulate.

313029282726252423222120191817161514131211109876543210
01000101size0Zm11010TZnZda
Decode fields Instruction Details
size T
0x 0 ADCLB
0x 1 ADCLT
1x 0 SBCLB
1x 1 SBCLT

SVE2 bitwise shift right and accumulate

These instructions are under SVE2 Accumulate.

313029282726252423222120191817161514131211109876543210
01000101tszh0tszlimm31110RUZnZda
Decode fields Instruction Details
R U
0 0 SSRA
0 1 USRA
1 0 SRSRA
1 1 URSRA

SVE2 bitwise shift and insert

These instructions are under SVE2 Accumulate.

313029282726252423222120191817161514131211109876543210
01000101tszh0tszlimm311110opZnZd
Decode fields Instruction Details
op
0 SRI
1 SLI

SVE2 integer absolute difference and accumulate

These instructions are under SVE2 Accumulate.

313029282726252423222120191817161514131211109876543210
01000101size0Zm11111UZnZda
Decode fields Instruction Details
U
0 SABA
1 UABA

SVE2 Narrowing

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01000101op01op1op20op3op4op5
Decode fieldsInstruction details
op0op1op2op3op4op5
0 00 0 10 SVE2 saturating extract narrow
0 00 1 10 0 0 SME2 multi-vec extract narrow
0 00 1 10 0 1 UNALLOCATED
0 00 1 10 1 UNALLOCATED
0 != 00 10 UNALLOCATED
0 0x SVE2 bitwise shift right narrow
1 0x 0 0 SME2 multi-vec shift narrow
1 0x 0 1 UNALLOCATED
1 0x 1 UNALLOCATED
1 10 UNALLOCATED
11 SVE2 integer add/subtract narrow high part

SVE2 saturating extract narrow

These instructions are under SVE2 Narrowing.

313029282726252423222120191817161514131211109876543210
010001010tszh1tszl000010opcTZnZd
Decode fields Instruction Details
opc T
00 0 SQXTNB
00 1 SQXTNT
01 0 UQXTNB
01 1 UQXTNT
10 0 SQXTUNB
10 1 SQXTUNT
11 UNALLOCATED

SME2 multi-vec extract narrow

These instructions are under SVE2 Narrowing.

313029282726252423222120191817161514131211109876543210
010001010tszh1tszl001010opc0Zn0Zd
Decode fields Instruction Details Feature
tszh tszl opc
0 0x UNALLOCATED-
0 10 00 SQCVTNFEAT_SVE2p1
0 10 01 UQCVTNFEAT_SVE2p1
0 10 10 SQCVTUNFEAT_SVE2p1
0 10 11 UNALLOCATED-
0 11 UNALLOCATED-
1 UNALLOCATED-

SVE2 bitwise shift right narrow

These instructions are under SVE2 Narrowing.

313029282726252423222120191817161514131211109876543210
010001010tszh1tszlimm300opURTZnZd
Decode fields Instruction Details
op U R T
0 0 0 0 SQSHRUNB
0 0 0 1 SQSHRUNT
0 0 1 0 SQRSHRUNB
0 0 1 1 SQRSHRUNT
0 1 0 0 SHRNB
0 1 0 1 SHRNT
0 1 1 0 RSHRNB
0 1 1 1 RSHRNT
1 0 0 0 SQSHRNB
1 0 0 1 SQSHRNT
1 0 1 0 SQRSHRNB
1 0 1 1 SQRSHRNT
1 1 0 0 UQSHRNB
1 1 0 1 UQSHRNT
1 1 1 0 UQRSHRNB
1 1 1 1 UQRSHRNT

SME2 multi-vec shift narrow

These instructions are under SVE2 Narrowing.

313029282726252423222120191817161514131211109876543210
010001011tszh1tszlimm400opUR0Zn0Zd
Decode fields Instruction Details Feature
tszh tszl op U R
0 0 UNALLOCATED-
0 1 0 0 0 UNALLOCATED-
0 1 0 0 1 SQRSHRUNFEAT_SVE2p1
0 1 0 1 UNALLOCATED-
0 1 1 0 UNALLOCATED-
0 1 1 0 1 SQRSHRNFEAT_SVE2p1
0 1 1 1 1 UQRSHRNFEAT_SVE2p1
1 UNALLOCATED-

SVE2 integer add/subtract narrow high part

These instructions are under SVE2 Narrowing.

313029282726252423222120191817161514131211109876543210
01000101size1Zm011SRTZnZd
Decode fields Instruction Details
S R T
0 0 0 ADDHNB
0 0 1 ADDHNT
0 1 0 RADDHNB
0 1 1 RADDHNT
1 0 0 SUBHNB
1 0 1 SUBHNT
1 1 0 RSUBHNB
1 1 1 RSUBHNT

SVE2 character match

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01000101size1Zm100PgZnopPd
Decode fields Instruction Details
op
0 MATCH
1 NMATCH

SVE2 Histogram Computation (Segment) and Lookup Table

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01000101op01101op1
Decode fieldsInstruction detailsFeature
op0op1
0 0x1 UNALLOCATED-
1 001 LUTI4Byte, single register tableFEAT_LUT
1 011 UNALLOCATED-
000 HISTSEG-
100 LUTI2ByteFEAT_LUT
1x1 SVE2 lookup table with 4-bit indices and 16-bit element size-
x10 LUTI2HalfwordFEAT_LUT

SVE2 lookup table with 4-bit indices and 16-bit element size

These instructions are under SVE2 Histogram Computation (Segment) and Lookup Table.

313029282726252423222120191817161514131211109876543210
01000101i21Zm1011op1ZnZd
Decode fields Instruction Details Feature
op
0 LUTI4halfword, two register tableFEAT_LUT
1 LUTI4halfword, single register tableFEAT_LUT

SVE2 Crypto Extensions

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
010001011op0op1111op2op3
Decode fieldsInstruction details
op0op1op2op3
000 00 00 00000 SVE2 crypto unary operations
000 00 00 != 00000 UNALLOCATED
000 00 x1 UNALLOCATED
000 01 0x UNALLOCATED
000 01 11 UNALLOCATED
000 1x 00 SVE2 crypto destructive binary operations
000 1x x1 UNALLOCATED
!= 000 0x UNALLOCATED
!= 000 11 UNALLOCATED
10 SVE2 crypto constructive binary operations

SVE2 crypto unary operations

These instructions are under SVE2 Crypto Extensions.

313029282726252423222120191817161514131211109876543210
01000101size10000011100op00000Zdn
Decode fields Instruction Details Feature
size op
00 0 AESMCFEAT_SVE_AES
00 1 AESIMCFEAT_SVE_AES
01 UNALLOCATED-
1x UNALLOCATED-

SVE2 crypto destructive binary operations

These instructions are under SVE2 Crypto Extensions.

313029282726252423222120191817161514131211109876543210
01000101size10001op11100o2ZmZdn
Decode fields Instruction Details Feature
size op o2
00 0 0 AESEFEAT_SVE_AES
00 0 1 AESDFEAT_SVE_AES
00 1 0 SM4EFEAT_SVE_SM4
00 1 1 UNALLOCATED-
01 UNALLOCATED-
1x UNALLOCATED-

SVE2 crypto constructive binary operations

These instructions are under SVE2 Crypto Extensions.

313029282726252423222120191817161514131211109876543210
01000101size1Zm11110opZnZd
Decode fields Instruction Details Feature
size op
00 0 SM4EKEYFEAT_SVE_SM4
00 1 RAX1FEAT_SVE_SHA3
01 UNALLOCATED-
1x UNALLOCATED-

SVE floating-point convert precision odd elements

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01100100opc0010opc2101PgZnZd
Decode fields Instruction Details Feature
opc opc2
x0 11 UNALLOCATED-
00 0x UNALLOCATED-
00 10 FCVTXNT-
01 UNALLOCATED-
10 00 FCVTNT (predicated)single-precision to half-precision-
10 01 FCVTLThalf-precision to single-precision-
10 10 BFCVTNTFEAT_BF16
11 0x UNALLOCATED-
11 10 FCVTNT (predicated)double-precision to single-precision-
11 11 FCVTLTsingle-precision to double-precision-

SVE2 floating-point pairwise operations

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01100100size010opc100PgZmZdn
Decode fields Instruction Details
opc
000 FADDP
001 UNALLOCATED
01x UNALLOCATED
100 FMAXNMP
101 FMINNMP
110 FMAXP
111 FMINP

SVE floating-point recursive reduction (quadwords)

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01100100size010opc101PgZnVd
Decode fields Instruction Details Feature
opc
000 FADDQVFEAT_SVE2p1
001 UNALLOCATED-
01x UNALLOCATED-
100 FMAXNMQVFEAT_SVE2p1
101 FMINNMQVFEAT_SVE2p1
110 FMAXQVFEAT_SVE2p1
111 FMINQVFEAT_SVE2p1

SVE floating-point multiply-add (indexed)

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01100100size1opc0000o2opZnZda
Decode fields Instruction Details Feature
size o2 op
0x 0 0 FMLA (indexed)half-precision-
0x 0 1 FMLS (indexed)half-precision-
0x 1 0 BFMLA (indexed)FEAT_SVE_B16B16
0x 1 1 BFMLS (indexed)FEAT_SVE_B16B16
1x 1 UNALLOCATED-
10 0 0 FMLA (indexed)single-precision-
10 0 1 FMLS (indexed)single-precision-
11 0 0 FMLA (indexed)double-precision-
11 0 1 FMLS (indexed)double-precision-

SVE floating-point complex multiply-add (indexed)

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01100100size1opc0001rotZnZda
Decode fields Instruction Details
size
0x UNALLOCATED
10 FCMLA (indexed)half-precision
11 FCMLA (indexed)single-precision

SVE floating-point multiply (indexed)

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01100100size1opc0010o20ZnZd
Decode fields Instruction Details Feature
size o2
0x 0 FMUL (indexed)half-precision-
0x 1 BFMUL (indexed)FEAT_SVE_B16B16
1x 1 UNALLOCATED-
10 0 FMUL (indexed)single-precision-
11 0 FMUL (indexed)double-precision-

SVE FP clamp

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01100100size1Zm001001ZnZd
Decode fields Instruction Details Feature
size
!= 00 FCLAMPFEAT_SVE2p1
00 BFCLAMPFEAT_SVE_B16B16

SVE Floating Point Widening Multiply-Add - Indexed

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01100100op0101op10
Decode fieldsInstruction details
op0op1
0 0 SVE BFloat16 floating-point dot product (indexed)
0 1 UNALLOCATED
1 SVE floating-point multiply-add long (indexed)

SVE BFloat16 floating-point dot product (indexed)

These instructions are under SVE Floating Point Widening Multiply-Add - Indexed.

313029282726252423222120191817161514131211109876543210
011001000op1i2Zm0100opc2ZnZda
Decode fields Instruction Details Feature
op opc2
0 x1 FDOT (2-way, indexed, FP8 to FP16)FEAT_FP8DOT2
0 00 FDOT (2-way, indexed, FP16 to FP32)FEAT_SVE2p1
0 10 UNALLOCATED-
1 00 BFDOT (indexed)FEAT_BF16
1 01 FDOT (4-way, indexed)FEAT_FP8DOT4
1 1x UNALLOCATED-

SVE floating-point multiply-add long (indexed)

These instructions are under SVE Floating Point Widening Multiply-Add - Indexed.

313029282726252423222120191817161514131211109876543210
011001001o21i3hZm01op0i3lTZnZda
Decode fields Instruction Details Feature
o2 op T
0 0 0 FMLALB (indexed, FP16 to FP32)-
0 0 1 FMLALT (indexed, FP16 to FP32)-
0 1 0 FMLSLB (indexed)-
0 1 1 FMLSLT (indexed)-
1 0 0 BFMLALB (indexed)FEAT_BF16
1 0 1 BFMLALT (indexed)FEAT_BF16
1 1 0 BFMLSLB (indexed)FEAT_SVE2p1
1 1 1 BFMLSLT (indexed)FEAT_SVE2p1

SVE Floating Point Widening Multiply-Add

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01100100op0110op100
Decode fieldsInstruction details
op0op1
0 0 SVE BFloat16 floating-point dot product
0 1 UNALLOCATED
1 SVE floating-point multiply-add long

SVE BFloat16 floating-point dot product

These instructions are under SVE Floating Point Widening Multiply-Add.

313029282726252423222120191817161514131211109876543210
011001000op1Zm10000o2ZnZda
Decode fields Instruction Details Feature
op o2
0 0 FDOT (2-way, vectors, FP16 to FP32)FEAT_SVE2p1
0 1 FDOT (2-way, vectors, FP8 to FP16)FEAT_FP8DOT2
1 0 BFDOT (vectors)FEAT_BF16
1 1 FDOT (4-way, vectors)FEAT_FP8DOT4

SVE floating-point multiply-add long

These instructions are under SVE Floating Point Widening Multiply-Add.

313029282726252423222120191817161514131211109876543210
011001001o21Zm10op00TZnZda
Decode fields Instruction Details Feature
o2 op T
0 0 0 FMLALB (vectors, FP16 to FP32)-
0 0 1 FMLALT (vectors, FP16 to FP32)-
0 1 0 FMLSLB (vectors)-
0 1 1 FMLSLT (vectors)-
1 0 0 BFMLALB (vectors)FEAT_BF16
1 0 1 BFMLALT (vectors)FEAT_BF16
1 1 0 BFMLSLB (vectors)FEAT_SVE2p1
1 1 1 BFMLSLT (vectors)FEAT_SVE2p1

SVE2 FP8 multiply-add long long (indexed)

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01100100TT1i4hZm1100i4lZnZda
Decode fields Instruction Details Feature
TT
00 FMLALLBB (indexed)FEAT_FP8FMA
01 FMLALLBT (indexed)FEAT_FP8FMA
10 FMLALLTB (indexed)FEAT_FP8FMA
11 FMLALLTT (indexed)FEAT_FP8FMA

SVE floating point matrix multiply accumulate

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01100100opc1Zm111001ZnZda
Decode fields Instruction Details Feature
opc
00 UNALLOCATED-
01 BFMMLAFEAT_BF16
10 FMMLA32-bit elementFEAT_F32MM
11 FMMLA64-bit elementFEAT_F64MM

SVE2 FP8 multiply-add long (indexed)

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01100100T01i4hZm0101i4lZnZda
Decode fields Instruction Details Feature
T
0 FMLALB (indexed, FP8 to FP16)FEAT_FP8FMA
1 FMLALT (indexed, FP8 to FP16)FEAT_FP8FMA

SVE2 FP8 Widening Multiply-Add

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01100100op00110op110
Decode fieldsInstruction details
op0op1
0 SVE2 FP8 multiply-add long long
1 0 SVE2 FP8 multiply-add long
1 1 UNALLOCATED

SVE2 FP8 multiply-add long long

These instructions are under SVE2 FP8 Widening Multiply-Add.

313029282726252423222120191817161514131211109876543210
01100100001Zm10TT10ZnZda
Decode fields Instruction Details Feature
TT
00 FMLALLBB (vectors)FEAT_FP8FMA
01 FMLALLBT (vectors)FEAT_FP8FMA
10 FMLALLTB (vectors)FEAT_FP8FMA
11 FMLALLTT (vectors)FEAT_FP8FMA

SVE2 FP8 multiply-add long

These instructions are under SVE2 FP8 Widening Multiply-Add.

313029282726252423222120191817161514131211109876543210
01100100101Zm100T10ZnZda
Decode fields Instruction Details Feature
T
0 FMLALB (vectors, FP8 to FP16)FEAT_FP8FMA
1 FMLALT (vectors, FP8 to FP16)FEAT_FP8FMA

SVE floating-point compare vectors

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01100101size0Zmop1o2PgZno3Pd
Decode fields Instruction Details
op o2 o3
0 0 0 FCM<cc> (vectors)FCMGE
0 0 1 FCM<cc> (vectors)FCMGT
0 1 0 FCM<cc> (vectors)FCMEQ
0 1 1 FCM<cc> (vectors)FCMNE
1 0 0 FCM<cc> (vectors)FCMUO
1 0 1 FAC<cc>FACGE
1 1 0 UNALLOCATED
1 1 1 FAC<cc>FACGT

SVE floating-point arithmetic (unpredicated)

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01100101size0Zm000opcZnZd
Decode fields Instruction Details Feature
size opc
011 FTSMUL-
10x UNALLOCATED-
110 FRECPS-
111 FRSQRTS-
!= 00 000 FADD (vectors, unpredicated)-
!= 00 001 FSUB (vectors, unpredicated)-
!= 00 010 FMUL (vectors, unpredicated)-
00 000 BFADD (unpredicated)FEAT_SVE_B16B16
00 001 BFSUB (unpredicated)FEAT_SVE_B16B16
00 010 BFMUL (vectors, unpredicated)FEAT_SVE_B16B16

SVE Floating Point Arithmetic - Predicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
011001010op0100op1op2
Decode fieldsInstruction details
op0op1op2
0x SVE floating-point arithmetic (predicated)
10 000 FTMAD
10 != 000 UNALLOCATED
11 0000 SVE floating-point arithmetic with immediate (predicated)
11 != 0000 UNALLOCATED

SVE floating-point arithmetic (predicated)

These instructions are under SVE Floating Point Arithmetic - Predicated.

313029282726252423222120191817161514131211109876543210
01100101size00opc100PgZmZdn
Decode fields Instruction Details Feature
size opc
0011 FSUBR (vectors)-
1000 FABD-
1001 FSCALE-
1010 FMULX-
1011 UNALLOCATED-
1100 FDIVR-
1101 FDIV-
1110 FAMAXFEAT_FAMINMAX
1111 FAMINFEAT_FAMINMAX
!= 00 0000 FADD (vectors, predicated)-
!= 00 0001 FSUB (vectors, predicated)-
!= 00 0010 FMUL (vectors, predicated)-
!= 00 0100 FMAXNM (vectors)-
!= 00 0101 FMINNM (vectors)-
!= 00 0110 FMAX (vectors)-
!= 00 0111 FMIN (vectors)-
00 0000 BFADD (predicated)FEAT_SVE_B16B16
00 0001 BFSUB (predicated)FEAT_SVE_B16B16
00 0010 BFMUL (vectors, predicated)FEAT_SVE_B16B16
00 0100 BFMAXNMFEAT_SVE_B16B16
00 0101 BFMINNMFEAT_SVE_B16B16
00 0110 BFMAXFEAT_SVE_B16B16
00 0111 BFMINFEAT_SVE_B16B16

SVE floating-point arithmetic with immediate (predicated)

These instructions are under SVE Floating Point Arithmetic - Predicated.

313029282726252423222120191817161514131211109876543210
01100101size011opc100Pg0000i1Zdn
Decode fields Instruction Details
opc
000 FADD (immediate)
001 FSUB (immediate)
010 FMUL (immediate)
011 FSUBR (immediate)
100 FMAXNM (immediate)
101 FMINNM (immediate)
110 FMAX (immediate)
111 FMIN (immediate)

SVE Floating Point Unary Operations - Predicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
011001010op0101
Decode fieldsInstruction details
op0
00x SVE floating-point round to integral value
010 SVE floating-point convert precision
011 SVE floating-point unary operations
10x SVE integer convert to floating-point
11x SVE floating-point convert to integer

SVE floating-point round to integral value

These instructions are under SVE Floating Point Unary Operations - Predicated.

313029282726252423222120191817161514131211109876543210
01100101size000opc101PgZnZd
Decode fields Instruction Details
opc
000 FRINT<r>nearest with ties to even
001 FRINT<r>toward plus infinity
010 FRINT<r>toward minus infinity
011 FRINT<r>toward zero
100 FRINT<r>nearest with ties to away
101 UNALLOCATED
110 FRINT<r>current mode signalling inexact
111 FRINT<r>current mode

SVE floating-point convert precision

These instructions are under SVE Floating Point Unary Operations - Predicated.

313029282726252423222120191817161514131211109876543210
01100101opc0010opc2101PgZnZd
Decode fields Instruction Details Feature
opc opc2
x0 11 UNALLOCATED-
00 0x UNALLOCATED-
00 10 FCVTX-
01 UNALLOCATED-
10 00 FCVTsingle-precision to half-precision-
10 01 FCVThalf-precision to single-precision-
10 10 BFCVTFEAT_BF16
11 00 FCVTdouble-precision to half-precision-
11 01 FCVThalf-precision to double-precision-
11 10 FCVTdouble-precision to single-precision-
11 11 FCVTsingle-precision to double-precision-

SVE floating-point unary operations

These instructions are under SVE Floating Point Unary Operations - Predicated.

313029282726252423222120191817161514131211109876543210
01100101size0011opc101PgZnZd
Decode fields Instruction Details
opc
00 FRECPX
01 FSQRT
1x UNALLOCATED

SVE integer convert to floating-point

These instructions are under SVE Floating Point Unary Operations - Predicated.

313029282726252423222120191817161514131211109876543210
01100101opc010opc2U101PgZnZd
Decode fields Instruction Details
opc opc2 U
00 UNALLOCATED
01 00 UNALLOCATED
01 01 0 SCVTF16-bit to half-precision
01 01 1 UCVTF16-bit to half-precision
01 10 0 SCVTF32-bit to half-precision
01 10 1 UCVTF32-bit to half-precision
01 11 0 SCVTF64-bit to half-precision
01 11 1 UCVTF64-bit to half-precision
10 0x UNALLOCATED
10 10 0 SCVTF32-bit to single-precision
10 10 1 UCVTF32-bit to single-precision
10 11 UNALLOCATED
11 00 0 SCVTF32-bit to double-precision
11 00 1 UCVTF32-bit to double-precision
11 01 UNALLOCATED
11 10 0 SCVTF64-bit to single-precision
11 10 1 UCVTF64-bit to single-precision
11 11 0 SCVTF64-bit to double-precision
11 11 1 UCVTF64-bit to double-precision

SVE floating-point convert to integer

These instructions are under SVE Floating Point Unary Operations - Predicated.

313029282726252423222120191817161514131211109876543210
01100101opc011opc2U101PgZnZd
Decode fields Instruction Details
opc opc2 U
00 0 FLOGB
00 1 UNALLOCATED
01 00 UNALLOCATED
01 01 0 FCVTZShalf-precision to 16-bit
01 01 1 FCVTZUhalf-precision to 16-bit
01 10 0 FCVTZShalf-precision to 32-bit
01 10 1 FCVTZUhalf-precision to 32-bit
01 11 0 FCVTZShalf-precision to 64-bit
01 11 1 FCVTZUhalf-precision to 64-bit
10 0x UNALLOCATED
10 10 0 FCVTZSsingle-precision to 32-bit
10 10 1 FCVTZUsingle-precision to 32-bit
10 11 UNALLOCATED
11 00 0 FCVTZSdouble-precision to 32-bit
11 00 1 FCVTZUdouble-precision to 32-bit
11 01 UNALLOCATED
11 10 0 FCVTZSsingle-precision to 64-bit
11 10 1 FCVTZUsingle-precision to 64-bit
11 11 0 FCVTZSdouble-precision to 64-bit
11 11 1 FCVTZUdouble-precision to 64-bit

SVE floating-point recursive reduction

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01100101size000opc001PgZnVd
Decode fields Instruction Details
opc
000 FADDV
001 UNALLOCATED
01x UNALLOCATED
100 FMAXNMV
101 FMINNMV
110 FMAXV
111 FMINV

SVE Floating Point Unary Operations - Unpredicated

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01100101op0001op10011op2op3
Decode fieldsInstruction details
op0op1op2op3
00 00x SVE2 FP8 upconverts
00 010 0 SVE2 FP8 downconverts
00 010 1 UNALLOCATED
00 011 UNALLOCATED
!= 00 0xx UNALLOCATED
10x UNALLOCATED
11x 00 SVE floating-point reciprocal estimate (unpredicated)
11x != 00 UNALLOCATED

SVE2 FP8 upconverts

These instructions are under SVE Floating Point Unary Operations - Unpredicated.

313029282726252423222120191817161514131211109876543210
011001010000100L0011opcZnZd
Decode fields Instruction Details Feature
L opc
0 00 F1CVT, F2CVTF1CVTFEAT_FP8
0 01 F1CVT, F2CVTF2CVTFEAT_FP8
0 10 BF1CVT, BF2CVTBF1CVTFEAT_FP8
0 11 BF1CVT, BF2CVTBF2CVTFEAT_FP8
1 00 F1CVTLT, F2CVTLTF1CVTLTFEAT_FP8
1 01 F1CVTLT, F2CVTLTF2CVTLTFEAT_FP8
1 10 BF1CVTLT, BF2CVTLTBF1CVTLTFEAT_FP8
1 11 BF1CVTLT, BF2CVTLTBF2CVTLTFEAT_FP8

SVE2 FP8 downconverts

These instructions are under SVE Floating Point Unary Operations - Unpredicated.

313029282726252423222120191817161514131211109876543210
01100101000010100011opcZn0Zd
Decode fields Instruction Details Feature
opc
00 FCVTNFEAT_FP8
01 FCVTNBFEAT_FP8
10 BFCVTNFEAT_FP8
11 FCVTNT (unpredicated)FEAT_FP8

SVE floating-point reciprocal estimate (unpredicated)

These instructions are under SVE Floating Point Unary Operations - Unpredicated.

313029282726252423222120191817161514131211109876543210
01100101size00111op001100ZnZd
Decode fields Instruction Details
op
0 FRECPE
1 FRSQRTE

SVE Floating Point Compare - with Zero

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01100101010op0001
Decode fieldsInstruction details
op0
0 SVE floating-point compare with zero
1 UNALLOCATED

SVE floating-point compare with zero

These instructions are under SVE Floating Point Compare - with Zero.

313029282726252423222120191817161514131211109876543210
01100101size0100eqlt001PgZnnePd
Decode fields Instruction Details
eq lt ne
0 0 0 FCM<cc> (zero)FCMGE
0 0 1 FCM<cc> (zero)FCMGT
0 1 0 FCM<cc> (zero)FCMLT
0 1 1 FCM<cc> (zero)FCMLE
1 1 UNALLOCATED
1 0 0 FCM<cc> (zero)FCMEQ
1 1 0 FCM<cc> (zero)FCMNE

SVE Floating Point Accumulating Reduction

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
01100101011op0001
Decode fieldsInstruction details
op0
0 SVE floating-point serial reduction (predicated)
1 UNALLOCATED

SVE floating-point serial reduction (predicated)

These instructions are under SVE Floating Point Accumulating Reduction.

313029282726252423222120191817161514131211109876543210
01100101size0110opc001PgZmVdn
Decode fields Instruction Details
opc
00 FADDA
01 UNALLOCATED
1x UNALLOCATED

SVE Floating Point Multiply-Add

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
011001011op0
Decode fieldsInstruction details
op0
0 SVE floating-point multiply-accumulate writing addend
1 SVE floating-point multiply-accumulate writing multiplicand

SVE floating-point multiply-accumulate writing addend

These instructions are under SVE Floating Point Multiply-Add.

313029282726252423222120191817161514131211109876543210
01100101size1Zm0opcPgZnZda
Decode fields Instruction Details Feature
size opc
10 FNMLA-
11 FNMLS-
!= 00 00 FMLA (vectors)-
!= 00 01 FMLS (vectors)-
00 00 BFMLA (vectors)FEAT_SVE_B16B16
00 01 BFMLS (vectors)FEAT_SVE_B16B16

SVE floating-point multiply-accumulate writing multiplicand

These instructions are under SVE Floating Point Multiply-Add.

313029282726252423222120191817161514131211109876543210
01100101size1Za1opcPgZmZdn
Decode fields Instruction Details
opc
00 FMAD
01 FMSB
10 FNMAD
11 FNMSB

SVE Memory - 32-bit Gather and Unsized Contiguous

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
1000010op0op1op2op3
Decode fieldsInstruction details
op0op1op2op3
00 x1 0xx 0 SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets)
00 x1 0xx 1 UNALLOCATED
01 x1 0xx SVE 32-bit gather load halfwords (scalar plus 32-bit scaled offsets)
10 x1 0xx SVE 32-bit gather load words (scalar plus 32-bit scaled offsets)
11 0x 000 0 LDR (predicate)
11 0x 000 1 UNALLOCATED
11 0x 010 LDR (vector)
11 0x 0x1 UNALLOCATED
11 1x 0xx 0 SVE contiguous prefetch (scalar plus immediate)
11 1x 0xx 1 UNALLOCATED
!= 11 x0 0xx SVE 32-bit gather load (scalar plus 32-bit unscaled offsets)
00 10x SVE2 32-bit gather non-temporal load (vector plus scalar)
00 110 0 SVE contiguous prefetch (scalar plus scalar)
00 111 0 SVE 32-bit gather prefetch (vector plus immediate)
00 11x 1 UNALLOCATED
01 1xx SVE 32-bit gather load (vector plus immediate)
1x 1xx SVE load and broadcast element

SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets)

These instructions are under SVE Memory - 32-bit Gather and Unsized Contiguous.

313029282726252423222120191817161514131211109876543210
100001000xs1Zm0mszPgRn0prfop
Decode fields Instruction Details
msz
00 PRFB (scalar plus vector)
01 PRFH (scalar plus vector)
10 PRFW (scalar plus vector)
11 PRFD (scalar plus vector)

SVE 32-bit gather load halfwords (scalar plus 32-bit scaled offsets)

These instructions are under SVE Memory - 32-bit Gather and Unsized Contiguous.

313029282726252423222120191817161514131211109876543210
100001001xs1Zm0UffPgRnZt
Decode fields Instruction Details
U ff
0 0 LD1SH (scalar plus vector)
0 1 LDFF1SH (scalar plus vector)
1 0 LD1H (scalar plus vector)
1 1 LDFF1H (scalar plus vector)

SVE 32-bit gather load words (scalar plus 32-bit scaled offsets)

These instructions are under SVE Memory - 32-bit Gather and Unsized Contiguous.

313029282726252423222120191817161514131211109876543210
100001010xs1Zm0UffPgRnZt
Decode fields Instruction Details
U ff
0 UNALLOCATED
1 0 LD1W (scalar plus vector)
1 1 LDFF1W (scalar plus vector)

SVE contiguous prefetch (scalar plus immediate)

These instructions are under SVE Memory - 32-bit Gather and Unsized Contiguous.

313029282726252423222120191817161514131211109876543210
1000010111imm60mszPgRn0prfop
Decode fields Instruction Details
msz
00 PRFB (scalar plus immediate)
01 PRFH (scalar plus immediate)
10 PRFW (scalar plus immediate)
11 PRFD (scalar plus immediate)

SVE 32-bit gather load (scalar plus 32-bit unscaled offsets)

These instructions are under SVE Memory - 32-bit Gather and Unsized Contiguous.

313029282726252423222120191817161514131211109876543210
1000010!= 11xs0Zm0UffPgRnZt
opc

The following constraints also apply to this encoding: opc != 11 && opc != 11

Decode fields Instruction Details
opc U ff
00 0 0 LD1SB (scalar plus vector)
00 0 1 LDFF1SB (scalar plus vector)
00 1 0 LD1B (scalar plus vector)
00 1 1 LDFF1B (scalar plus vector)
01 0 0 LD1SH (scalar plus vector)
01 0 1 LDFF1SH (scalar plus vector)
01 1 0 LD1H (scalar plus vector)
01 1 1 LDFF1H (scalar plus vector)
10 0 UNALLOCATED
10 1 0 LD1W (scalar plus vector)
10 1 1 LDFF1W (scalar plus vector)

SVE2 32-bit gather non-temporal load (vector plus scalar)

These instructions are under SVE Memory - 32-bit Gather and Unsized Contiguous.

313029282726252423222120191817161514131211109876543210
1000010msz00Rm10UPgZnZt
Decode fields Instruction Details
msz U
00 0 LDNT1SB
00 1 LDNT1B (vector plus scalar)
01 0 LDNT1SH
01 1 LDNT1H (vector plus scalar)
10 0 UNALLOCATED
10 1 LDNT1W (vector plus scalar)
11 UNALLOCATED

SVE contiguous prefetch (scalar plus scalar)

These instructions are under SVE Memory - 32-bit Gather and Unsized Contiguous.

313029282726252423222120191817161514131211109876543210
1000010msz00Rm110PgRn0prfop
Decode fields Instruction Details
msz
00 PRFB (scalar plus scalar)
01 PRFH (scalar plus scalar)
10 PRFW (scalar plus scalar)
11 PRFD (scalar plus scalar)

SVE 32-bit gather prefetch (vector plus immediate)

These instructions are under SVE Memory - 32-bit Gather and Unsized Contiguous.

313029282726252423222120191817161514131211109876543210
1000010msz00imm5111PgZn0prfop
Decode fields Instruction Details
msz
00 PRFB (vector plus immediate)
01 PRFH (vector plus immediate)
10 PRFW (vector plus immediate)
11 PRFD (vector plus immediate)

SVE 32-bit gather load (vector plus immediate)

These instructions are under SVE Memory - 32-bit Gather and Unsized Contiguous.

313029282726252423222120191817161514131211109876543210
1000010msz01imm51UffPgZnZt
Decode fields Instruction Details
msz U ff
00 0 0 LD1SB (vector plus immediate)
00 0 1 LDFF1SB (vector plus immediate)
00 1 0 LD1B (vector plus immediate)
00 1 1 LDFF1B (vector plus immediate)
01 0 0 LD1SH (vector plus immediate)
01 0 1 LDFF1SH (vector plus immediate)
01 1 0 LD1H (vector plus immediate)
01 1 1 LDFF1H (vector plus immediate)
10 0 UNALLOCATED
10 1 0 LD1W (vector plus immediate)
10 1 1 LDFF1W (vector plus immediate)
11 UNALLOCATED

SVE load and broadcast element

These instructions are under SVE Memory - 32-bit Gather and Unsized Contiguous.

313029282726252423222120191817161514131211109876543210
1000010dtypeh1imm61dtypelPgRnZt
Decode fields Instruction Details
dtypeh dtypel
00 00 LD1RB8-bit element
00 01 LD1RB16-bit element
00 10 LD1RB32-bit element
00 11 LD1RB64-bit element
01 00 LD1RSW
01 01 LD1RH16-bit element
01 10 LD1RH32-bit element
01 11 LD1RH64-bit element
10 00 LD1RSH64-bit element
10 01 LD1RSH32-bit element
10 10 LD1RW32-bit element
10 11 LD1RW64-bit element
11 00 LD1RSB64-bit element
11 01 LD1RSB32-bit element
11 10 LD1RSB16-bit element
11 11 LD1RD

SVE Memory - Contiguous Load

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
1010010op0op1op2
Decode fieldsInstruction details
op0op1op2
00 0 111 SVE contiguous non-temporal load (scalar plus immediate)
00 1 001 SVE contiguous load (quadwords, scalar plus immediate)
00 1 111 SVE load multiple structures (quadwords, scalar plus immediate)
00 100 SVE contiguous load (quadwords, scalar plus scalar)
00 110 SVE contiguous non-temporal load (scalar plus scalar)
01 100 SVE load multiple structures (quadwords, scalar plus scalar)
1x 100 UNALLOCATED
!= 00 0 111 SVE load multiple structures (scalar plus immediate)
!= 00 1 001 UNALLOCATED
!= 00 1 111 UNALLOCATED
!= 00 110 SVE load multiple structures (scalar plus scalar)
0 001 SVE load and broadcast quadword (scalar plus immediate)
0 101 SVE contiguous load (scalar plus immediate)
1 101 SVE contiguous non-fault load (scalar plus immediate)
000 SVE load and broadcast quadword (scalar plus scalar)
010 SVE contiguous load (scalar plus scalar)
011 SVE contiguous first-fault load (scalar plus scalar)

SVE contiguous non-temporal load (scalar plus immediate)

These instructions are under SVE Memory - Contiguous Load.

313029282726252423222120191817161514131211109876543210
1010010msz000imm4111PgRnZt
Decode fields Instruction Details
msz
00 LDNT1B (scalar plus immediate, single register)
01 LDNT1H (scalar plus immediate, single register)
10 LDNT1W (scalar plus immediate, single register)
11 LDNT1D (scalar plus immediate, single register)

SVE contiguous load (quadwords, scalar plus immediate)

These instructions are under SVE Memory - Contiguous Load.

313029282726252423222120191817161514131211109876543210
1010010dtype001imm4001PgRnZt
Decode fields Instruction Details Feature
dtype
0x UNALLOCATED-
10 LD1W (scalar plus immediate, single register)FEAT_SVE2p1
11 LD1D (scalar plus immediate, single register)FEAT_SVE2p1

SVE load multiple structures (quadwords, scalar plus immediate)

These instructions are under SVE Memory - Contiguous Load.

313029282726252423222120191817161514131211109876543210
1010010num001imm4111PgRnZt
Decode fields Instruction Details Feature
num
00 UNALLOCATED-
01 LD2Q (scalar plus immediate)FEAT_SVE2p1
10 LD3Q (scalar plus immediate)FEAT_SVE2p1
11 LD4Q (scalar plus immediate)FEAT_SVE2p1

SVE contiguous load (quadwords, scalar plus scalar)

These instructions are under SVE Memory - Contiguous Load.

313029282726252423222120191817161514131211109876543210
1010010dtype00Rm100PgRnZt
Decode fields Instruction Details Feature
dtype
0x UNALLOCATED-
10 LD1W (scalar plus scalar, single register)FEAT_SVE2p1
11 LD1D (scalar plus scalar, single register)FEAT_SVE2p1

SVE contiguous non-temporal load (scalar plus scalar)

These instructions are under SVE Memory - Contiguous Load.

313029282726252423222120191817161514131211109876543210
1010010msz00Rm110PgRnZt
Decode fields Instruction Details
msz
00 LDNT1B (scalar plus scalar, single register)
01 LDNT1H (scalar plus scalar, single register)
10 LDNT1W (scalar plus scalar, single register)
11 LDNT1D (scalar plus scalar, single register)

SVE load multiple structures (quadwords, scalar plus scalar)

These instructions are under SVE Memory - Contiguous Load.

313029282726252423222120191817161514131211109876543210
1010010num01Rm100PgRnZt
Decode fields Instruction Details Feature
num
00 UNALLOCATED-
01 LD2Q (scalar plus scalar)FEAT_SVE2p1
10 LD3Q (scalar plus scalar)FEAT_SVE2p1
11 LD4Q (scalar plus scalar)FEAT_SVE2p1

SVE load multiple structures (scalar plus immediate)

These instructions are under SVE Memory - Contiguous Load.

313029282726252423222120191817161514131211109876543210
1010010msz!= 000imm4111PgRnZt
opc

The following constraints also apply to this encoding: opc != 00 && opc != 00

Decode fields Instruction Details
msz opc
00 01 LD2B (scalar plus immediate)
00 10 LD3B (scalar plus immediate)
00 11 LD4B (scalar plus immediate)
01 01 LD2H (scalar plus immediate)
01 10 LD3H (scalar plus immediate)
01 11 LD4H (scalar plus immediate)
10 01 LD2W (scalar plus immediate)
10 10 LD3W (scalar plus immediate)
10 11 LD4W (scalar plus immediate)
11 01 LD2D (scalar plus immediate)
11 10 LD3D (scalar plus immediate)
11 11 LD4D (scalar plus immediate)

SVE load multiple structures (scalar plus scalar)

These instructions are under SVE Memory - Contiguous Load.

313029282726252423222120191817161514131211109876543210
1010010msz!= 00Rm110PgRnZt
opc

The following constraints also apply to this encoding: opc != 00 && opc != 00

Decode fields Instruction Details
msz opc
00 01 LD2B (scalar plus scalar)
00 10 LD3B (scalar plus scalar)
00 11 LD4B (scalar plus scalar)
01 01 LD2H (scalar plus scalar)
01 10 LD3H (scalar plus scalar)
01 11 LD4H (scalar plus scalar)
10 01 LD2W (scalar plus scalar)
10 10 LD3W (scalar plus scalar)
10 11 LD4W (scalar plus scalar)
11 01 LD2D (scalar plus scalar)
11 10 LD3D (scalar plus scalar)
11 11 LD4D (scalar plus scalar)

SVE load and broadcast quadword (scalar plus immediate)

These instructions are under SVE Memory - Contiguous Load.

313029282726252423222120191817161514131211109876543210
1010010mszssz0imm4001PgRnZt
Decode fields Instruction Details Feature
msz ssz
1x UNALLOCATED-
00 00 LD1RQB (scalar plus immediate)-
00 01 LD1ROB (scalar plus immediate)FEAT_F64MM
01 00 LD1RQH (scalar plus immediate)-
01 01 LD1ROH (scalar plus immediate)FEAT_F64MM
10 00 LD1RQW (scalar plus immediate)-
10 01 LD1ROW (scalar plus immediate)FEAT_F64MM
11 00 LD1RQD (scalar plus immediate)-
11 01 LD1ROD (scalar plus immediate)FEAT_F64MM

SVE contiguous load (scalar plus immediate)

These instructions are under SVE Memory - Contiguous Load.

313029282726252423222120191817161514131211109876543210
1010010dtype0imm4101PgRnZt
Decode fields Instruction Details
dtype
0000 LD1B (scalar plus immediate, single register)8-bit element
0001 LD1B (scalar plus immediate, single register)16-bit element
0010 LD1B (scalar plus immediate, single register)32-bit element
0011 LD1B (scalar plus immediate, single register)64-bit element
0100 LD1SW (scalar plus immediate)
0101 LD1H (scalar plus immediate, single register)16-bit element
0110 LD1H (scalar plus immediate, single register)32-bit element
0111 LD1H (scalar plus immediate, single register)64-bit element
1000 LD1SH (scalar plus immediate)64-bit element
1001 LD1SH (scalar plus immediate)32-bit element
1010 LD1W (scalar plus immediate, single register)32-bit element
1011 LD1W (scalar plus immediate, single register)64-bit element
1100 LD1SB (scalar plus immediate)64-bit element
1101 LD1SB (scalar plus immediate)32-bit element
1110 LD1SB (scalar plus immediate)16-bit element
1111 LD1D (scalar plus immediate, single register)

SVE contiguous non-fault load (scalar plus immediate)

These instructions are under SVE Memory - Contiguous Load.

313029282726252423222120191817161514131211109876543210
1010010dtype1imm4101PgRnZt
Decode fields Instruction Details
dtype
0000 LDNF1B8-bit element
0001 LDNF1B16-bit element
0010 LDNF1B32-bit element
0011 LDNF1B64-bit element
0100 LDNF1SW
0101 LDNF1H16-bit element
0110 LDNF1H32-bit element
0111 LDNF1H64-bit element
1000 LDNF1SH64-bit element
1001 LDNF1SH32-bit element
1010 LDNF1W32-bit element
1011 LDNF1W64-bit element
1100 LDNF1SB64-bit element
1101 LDNF1SB32-bit element
1110 LDNF1SB16-bit element
1111 LDNF1D

SVE load and broadcast quadword (scalar plus scalar)

These instructions are under SVE Memory - Contiguous Load.

313029282726252423222120191817161514131211109876543210
1010010mszsszRm000PgRnZt
Decode fields Instruction Details Feature
msz ssz
1x UNALLOCATED-
00 00 LD1RQB (scalar plus scalar)-
00 01 LD1ROB (scalar plus scalar)FEAT_F64MM
01 00 LD1RQH (scalar plus scalar)-
01 01 LD1ROH (scalar plus scalar)FEAT_F64MM
10 00 LD1RQW (scalar plus scalar)-
10 01 LD1ROW (scalar plus scalar)FEAT_F64MM
11 00 LD1RQD (scalar plus scalar)-
11 01 LD1ROD (scalar plus scalar)FEAT_F64MM

SVE contiguous load (scalar plus scalar)

These instructions are under SVE Memory - Contiguous Load.

313029282726252423222120191817161514131211109876543210
1010010dtypeRm010PgRnZt
Decode fields Instruction Details
dtype
0000 LD1B (scalar plus scalar, single register)8-bit element
0001 LD1B (scalar plus scalar, single register)16-bit element
0010 LD1B (scalar plus scalar, single register)32-bit element
0011 LD1B (scalar plus scalar, single register)64-bit element
0100 LD1SW (scalar plus scalar)
0101 LD1H (scalar plus scalar, single register)16-bit element
0110 LD1H (scalar plus scalar, single register)32-bit element
0111 LD1H (scalar plus scalar, single register)64-bit element
1000 LD1SH (scalar plus scalar)64-bit element
1001 LD1SH (scalar plus scalar)32-bit element
1010 LD1W (scalar plus scalar, single register)32-bit element
1011 LD1W (scalar plus scalar, single register)64-bit element
1100 LD1SB (scalar plus scalar)64-bit element
1101 LD1SB (scalar plus scalar)32-bit element
1110 LD1SB (scalar plus scalar)16-bit element
1111 LD1D (scalar plus scalar, single register)

SVE contiguous first-fault load (scalar plus scalar)

These instructions are under SVE Memory - Contiguous Load.

313029282726252423222120191817161514131211109876543210
1010010dtypeRm011PgRnZt
Decode fields Instruction Details
dtype
0000 LDFF1B (scalar plus scalar)8-bit element
0001 LDFF1B (scalar plus scalar)16-bit element
0010 LDFF1B (scalar plus scalar)32-bit element
0011 LDFF1B (scalar plus scalar)64-bit element
0100 LDFF1SW (scalar plus scalar)
0101 LDFF1H (scalar plus scalar)16-bit element
0110 LDFF1H (scalar plus scalar)32-bit element
0111 LDFF1H (scalar plus scalar)64-bit element
1000 LDFF1SH (scalar plus scalar)64-bit element
1001 LDFF1SH (scalar plus scalar)32-bit element
1010 LDFF1W (scalar plus scalar)32-bit element
1011 LDFF1W (scalar plus scalar)64-bit element
1100 LDFF1SB (scalar plus scalar)64-bit element
1101 LDFF1SB (scalar plus scalar)32-bit element
1110 LDFF1SB (scalar plus scalar)16-bit element
1111 LDFF1D (scalar plus scalar)

SVE Memory - 64-bit Gather

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
1100010op0op1op2op3
Decode fieldsInstruction detailsFeature
op0op1op2op3
00 00 101 LD1QFEAT_SVE2p1
00 01 0xx 1 UNALLOCATED-
00 11 1xx 0 SVE 64-bit gather prefetch (scalar plus 64-bit scaled offsets)-
00 11 1 UNALLOCATED-
00 x1 0xx 0 SVE 64-bit gather prefetch (scalar plus unpacked 32-bit scaled offsets)-
!= 00 00 101 UNALLOCATED-
!= 00 11 1xx SVE 64-bit gather load (scalar plus 64-bit scaled offsets)-
!= 00 x1 0xx SVE 64-bit gather load (scalar plus 32-bit unpacked scaled offsets)-
00 111 0 SVE 64-bit gather prefetch (vector plus immediate)-
00 111 1 UNALLOCATED-
00 1x0 SVE2 64-bit gather non-temporal load (vector plus scalar)-
01 1xx SVE 64-bit gather load (vector plus immediate)-
10 1xx SVE 64-bit gather load (scalar plus 64-bit unscaled offsets)-
x0 0xx SVE 64-bit gather load (scalar plus unpacked 32-bit unscaled offsets)-

SVE 64-bit gather prefetch (scalar plus 64-bit scaled offsets)

These instructions are under SVE Memory - 64-bit Gather.

313029282726252423222120191817161514131211109876543210
11000100011Zm1mszPgRn0prfop
Decode fields Instruction Details
msz
00 PRFB (scalar plus vector)
01 PRFH (scalar plus vector)
10 PRFW (scalar plus vector)
11 PRFD (scalar plus vector)

SVE 64-bit gather prefetch (scalar plus unpacked 32-bit scaled offsets)

These instructions are under SVE Memory - 64-bit Gather.

313029282726252423222120191817161514131211109876543210
110001000xs1Zm0mszPgRn0prfop
Decode fields Instruction Details
msz
00 PRFB (scalar plus vector)
01 PRFH (scalar plus vector)
10 PRFW (scalar plus vector)
11 PRFD (scalar plus vector)

SVE 64-bit gather load (scalar plus 64-bit scaled offsets)

These instructions are under SVE Memory - 64-bit Gather.

313029282726252423222120191817161514131211109876543210
1100010!= 0011Zm1UffPgRnZt
opc

The following constraints also apply to this encoding: opc != 00 && opc != 00

Decode fields Instruction Details
opc U ff
01 0 0 LD1SH (scalar plus vector)
01 0 1 LDFF1SH (scalar plus vector)
01 1 0 LD1H (scalar plus vector)
01 1 1 LDFF1H (scalar plus vector)
10 0 0 LD1SW (scalar plus vector)
10 0 1 LDFF1SW (scalar plus vector)
10 1 0 LD1W (scalar plus vector)
10 1 1 LDFF1W (scalar plus vector)
11 0 UNALLOCATED
11 1 0 LD1D (scalar plus vector)
11 1 1 LDFF1D (scalar plus vector)

SVE 64-bit gather load (scalar plus 32-bit unpacked scaled offsets)

These instructions are under SVE Memory - 64-bit Gather.

313029282726252423222120191817161514131211109876543210
1100010!= 00xs1Zm0UffPgRnZt
opc

The following constraints also apply to this encoding: opc != 00 && opc != 00

Decode fields Instruction Details
opc U ff
01 0 0 LD1SH (scalar plus vector)
01 0 1 LDFF1SH (scalar plus vector)
01 1 0 LD1H (scalar plus vector)
01 1 1 LDFF1H (scalar plus vector)
10 0 0 LD1SW (scalar plus vector)
10 0 1 LDFF1SW (scalar plus vector)
10 1 0 LD1W (scalar plus vector)
10 1 1 LDFF1W (scalar plus vector)
11 0 UNALLOCATED
11 1 0 LD1D (scalar plus vector)
11 1 1 LDFF1D (scalar plus vector)

SVE 64-bit gather prefetch (vector plus immediate)

These instructions are under SVE Memory - 64-bit Gather.

313029282726252423222120191817161514131211109876543210
1100010msz00imm5111PgZn0prfop
Decode fields Instruction Details
msz
00 PRFB (vector plus immediate)
01 PRFH (vector plus immediate)
10 PRFW (vector plus immediate)
11 PRFD (vector plus immediate)

SVE2 64-bit gather non-temporal load (vector plus scalar)

These instructions are under SVE Memory - 64-bit Gather.

313029282726252423222120191817161514131211109876543210
1100010msz00Rm1U0PgZnZt
Decode fields Instruction Details
msz U
00 0 LDNT1SB
00 1 LDNT1B (vector plus scalar)
01 0 LDNT1SH
01 1 LDNT1H (vector plus scalar)
10 0 LDNT1SW
10 1 LDNT1W (vector plus scalar)
11 0 UNALLOCATED
11 1 LDNT1D (vector plus scalar)

SVE 64-bit gather load (vector plus immediate)

These instructions are under SVE Memory - 64-bit Gather.

313029282726252423222120191817161514131211109876543210
1100010msz01imm51UffPgZnZt
Decode fields Instruction Details
msz U ff
00 0 0 LD1SB (vector plus immediate)
00 0 1 LDFF1SB (vector plus immediate)
00 1 0 LD1B (vector plus immediate)
00 1 1 LDFF1B (vector plus immediate)
01 0 0 LD1SH (vector plus immediate)
01 0 1 LDFF1SH (vector plus immediate)
01 1 0 LD1H (vector plus immediate)
01 1 1 LDFF1H (vector plus immediate)
10 0 0 LD1SW (vector plus immediate)
10 0 1 LDFF1SW (vector plus immediate)
10 1 0 LD1W (vector plus immediate)
10 1 1 LDFF1W (vector plus immediate)
11 0 UNALLOCATED
11 1 0 LD1D (vector plus immediate)
11 1 1 LDFF1D (vector plus immediate)

SVE 64-bit gather load (scalar plus 64-bit unscaled offsets)

These instructions are under SVE Memory - 64-bit Gather.

313029282726252423222120191817161514131211109876543210
1100010msz10Zm1UffPgRnZt
Decode fields Instruction Details
msz U ff
00 0 0 LD1SB (scalar plus vector)
00 0 1 LDFF1SB (scalar plus vector)
00 1 0 LD1B (scalar plus vector)
00 1 1 LDFF1B (scalar plus vector)
01 0 0 LD1SH (scalar plus vector)
01 0 1 LDFF1SH (scalar plus vector)
01 1 0 LD1H (scalar plus vector)
01 1 1 LDFF1H (scalar plus vector)
10 0 0 LD1SW (scalar plus vector)
10 0 1 LDFF1SW (scalar plus vector)
10 1 0 LD1W (scalar plus vector)
10 1 1 LDFF1W (scalar plus vector)
11 0 UNALLOCATED
11 1 0 LD1D (scalar plus vector)
11 1 1 LDFF1D (scalar plus vector)

SVE 64-bit gather load (scalar plus unpacked 32-bit unscaled offsets)

These instructions are under SVE Memory - 64-bit Gather.

313029282726252423222120191817161514131211109876543210
1100010mszxs0Zm0UffPgRnZt
Decode fields Instruction Details
msz U ff
00 0 0 LD1SB (scalar plus vector)
00 0 1 LDFF1SB (scalar plus vector)
00 1 0 LD1B (scalar plus vector)
00 1 1 LDFF1B (scalar plus vector)
01 0 0 LD1SH (scalar plus vector)
01 0 1 LDFF1SH (scalar plus vector)
01 1 0 LD1H (scalar plus vector)
01 1 1 LDFF1H (scalar plus vector)
10 0 0 LD1SW (scalar plus vector)
10 0 1 LDFF1SW (scalar plus vector)
10 1 0 LD1W (scalar plus vector)
10 1 1 LDFF1W (scalar plus vector)
11 0 UNALLOCATED
11 1 0 LD1D (scalar plus vector)
11 1 1 LDFF1D (scalar plus vector)

SVE Memory - Contiguous Store and Unsized Contiguous

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
1110010op0op10op20op3
Decode fieldsInstruction details
op0op1op2op3
0xx 00 0 SVE store multiple structures (quadwords, scalar plus immediate)
0xx 01 0 UNALLOCATED
0xx 1x 0 SVE store multiple structures (quadwords, scalar plus scalar)
10x 0 UNALLOCATED
110 0 0 STR (predicate)
110 0 1 UNALLOCATED
110 1 STR (vector)
111 0 UNALLOCATED
!= 110 1 SVE contiguous store (scalar plus scalar)

SVE store multiple structures (quadwords, scalar plus immediate)

These instructions are under SVE Memory - Contiguous Store and Unsized Contiguous.

313029282726252423222120191817161514131211109876543210
11100100num00imm4000PgRnZt
Decode fields Instruction Details Feature
num
00 UNALLOCATED-
01 ST2Q (scalar plus immediate)FEAT_SVE2p1
10 ST3Q (scalar plus immediate)FEAT_SVE2p1
11 ST4Q (scalar plus immediate)FEAT_SVE2p1

SVE store multiple structures (quadwords, scalar plus scalar)

These instructions are under SVE Memory - Contiguous Store and Unsized Contiguous.

313029282726252423222120191817161514131211109876543210
11100100num1Rm000PgRnZt
Decode fields Instruction Details Feature
num
00 UNALLOCATED-
01 ST2Q (scalar plus scalar)FEAT_SVE2p1
10 ST3Q (scalar plus scalar)FEAT_SVE2p1
11 ST4Q (scalar plus scalar)FEAT_SVE2p1

SVE contiguous store (scalar plus scalar)

These instructions are under SVE Memory - Contiguous Store and Unsized Contiguous.

313029282726252423222120191817161514131211109876543210
1110010!= 110o2Rm010PgRnZt
opc

The following constraints also apply to this encoding: opc != 110 && opc != 110

Decode fields Instruction Details Feature
opc o2
00x ST1B (scalar plus scalar, single register)-
01x ST1H (scalar plus scalar, single register)-
100 0 ST1W (scalar plus scalar, single register)SVE2FEAT_SVE2p1
101 ST1W (scalar plus scalar, single register)SVE-
111 0 ST1D (scalar plus scalar, single register)SVE2FEAT_SVE2p1
111 1 ST1D (scalar plus scalar, single register)SVE-

SVE Memory - Non-temporal and Quadword Scatter Store

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
1110010op0op1001
Decode fieldsInstruction detailsFeature
op0op1
000 1 ST1QFEAT_SVE2p1
!= 000 1 UNALLOCATED-
xx0 0 SVE2 64-bit scatter non-temporal store (vector plus scalar)-
xx1 0 SVE2 32-bit scatter non-temporal store (vector plus scalar)-

SVE2 64-bit scatter non-temporal store (vector plus scalar)

These instructions are under SVE Memory - Non-temporal and Quadword Scatter Store.

313029282726252423222120191817161514131211109876543210
1110010msz00Rm001PgZnZt
Decode fields Instruction Details
msz
00 STNT1B (vector plus scalar)
01 STNT1H (vector plus scalar)
10 STNT1W (vector plus scalar)
11 STNT1D (vector plus scalar)

SVE2 32-bit scatter non-temporal store (vector plus scalar)

These instructions are under SVE Memory - Non-temporal and Quadword Scatter Store.

313029282726252423222120191817161514131211109876543210
1110010msz10Rm001PgZnZt
Decode fields Instruction Details
msz
00 STNT1B (vector plus scalar)
01 STNT1H (vector plus scalar)
10 STNT1W (vector plus scalar)
11 UNALLOCATED

SVE Memory - Non-temporal and Multi-register Contiguous Store

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
1110010op0011
Decode fieldsInstruction details
op0
00 SVE contiguous non-temporal store (scalar plus scalar)
!= 00 SVE store multiple structures (scalar plus scalar)

SVE contiguous non-temporal store (scalar plus scalar)

These instructions are under SVE Memory - Non-temporal and Multi-register Contiguous Store.

313029282726252423222120191817161514131211109876543210
1110010msz00Rm011PgRnZt
Decode fields Instruction Details
msz
00 STNT1B (scalar plus scalar, single register)
01 STNT1H (scalar plus scalar, single register)
10 STNT1W (scalar plus scalar, single register)
11 STNT1D (scalar plus scalar, single register)

SVE store multiple structures (scalar plus scalar)

These instructions are under SVE Memory - Non-temporal and Multi-register Contiguous Store.

313029282726252423222120191817161514131211109876543210
1110010msz!= 00Rm011PgRnZt
opc

The following constraints also apply to this encoding: opc != 00 && opc != 00

Decode fields Instruction Details
msz opc
00 01 ST2B (scalar plus scalar)
00 10 ST3B (scalar plus scalar)
00 11 ST4B (scalar plus scalar)
01 01 ST2H (scalar plus scalar)
01 10 ST3H (scalar plus scalar)
01 11 ST4H (scalar plus scalar)
10 01 ST2W (scalar plus scalar)
10 10 ST3W (scalar plus scalar)
10 11 ST4W (scalar plus scalar)
11 01 ST2D (scalar plus scalar)
11 10 ST3D (scalar plus scalar)
11 11 ST4D (scalar plus scalar)

SVE Memory - Scatter with Optional Sign Extend

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
1110010op010
Decode fieldsInstruction details
op0
00 SVE 64-bit scatter store (scalar plus unpacked 32-bit unscaled offsets)
01 SVE 64-bit scatter store (scalar plus unpacked 32-bit scaled offsets)
10 SVE 32-bit scatter store (scalar plus 32-bit unscaled offsets)
11 SVE 32-bit scatter store (scalar plus 32-bit scaled offsets)

SVE 64-bit scatter store (scalar plus unpacked 32-bit unscaled offsets)

These instructions are under SVE Memory - Scatter with Optional Sign Extend.

313029282726252423222120191817161514131211109876543210
1110010msz00Zm1xs0PgRnZt
Decode fields Instruction Details
msz
00 ST1B (scalar plus vector)
01 ST1H (scalar plus vector)
10 ST1W (scalar plus vector)
11 ST1D (scalar plus vector)

SVE 64-bit scatter store (scalar plus unpacked 32-bit scaled offsets)

These instructions are under SVE Memory - Scatter with Optional Sign Extend.

313029282726252423222120191817161514131211109876543210
1110010msz01Zm1xs0PgRnZt
Decode fields Instruction Details
msz
00 UNALLOCATED
01 ST1H (scalar plus vector)
10 ST1W (scalar plus vector)
11 ST1D (scalar plus vector)

SVE 32-bit scatter store (scalar plus 32-bit unscaled offsets)

These instructions are under SVE Memory - Scatter with Optional Sign Extend.

313029282726252423222120191817161514131211109876543210
1110010msz10Zm1xs0PgRnZt
Decode fields Instruction Details
msz
00 ST1B (scalar plus vector)
01 ST1H (scalar plus vector)
10 ST1W (scalar plus vector)
11 UNALLOCATED

SVE 32-bit scatter store (scalar plus 32-bit scaled offsets)

These instructions are under SVE Memory - Scatter with Optional Sign Extend.

313029282726252423222120191817161514131211109876543210
1110010msz11Zm1xs0PgRnZt
Decode fields Instruction Details
msz
00 UNALLOCATED
01 ST1H (scalar plus vector)
10 ST1W (scalar plus vector)
11 UNALLOCATED

SVE Memory - Scatter

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
1110010op0101
Decode fieldsInstruction details
op0
00 SVE 64-bit scatter store (scalar plus 64-bit unscaled offsets)
01 SVE 64-bit scatter store (scalar plus 64-bit scaled offsets)
10 SVE 64-bit scatter store (vector plus immediate)
11 SVE 32-bit scatter store (vector plus immediate)

SVE 64-bit scatter store (scalar plus 64-bit unscaled offsets)

These instructions are under SVE Memory - Scatter.

313029282726252423222120191817161514131211109876543210
1110010msz00Zm101PgRnZt
Decode fields Instruction Details
msz
00 ST1B (scalar plus vector)
01 ST1H (scalar plus vector)
10 ST1W (scalar plus vector)
11 ST1D (scalar plus vector)

SVE 64-bit scatter store (scalar plus 64-bit scaled offsets)

These instructions are under SVE Memory - Scatter.

313029282726252423222120191817161514131211109876543210
1110010msz01Zm101PgRnZt
Decode fields Instruction Details
msz
00 UNALLOCATED
01 ST1H (scalar plus vector)
10 ST1W (scalar plus vector)
11 ST1D (scalar plus vector)

SVE 64-bit scatter store (vector plus immediate)

These instructions are under SVE Memory - Scatter.

313029282726252423222120191817161514131211109876543210
1110010msz10imm5101PgZnZt
Decode fields Instruction Details
msz
00 ST1B (vector plus immediate)
01 ST1H (vector plus immediate)
10 ST1W (vector plus immediate)
11 ST1D (vector plus immediate)

SVE 32-bit scatter store (vector plus immediate)

These instructions are under SVE Memory - Scatter.

313029282726252423222120191817161514131211109876543210
1110010msz11imm5101PgZnZt
Decode fields Instruction Details
msz
00 ST1B (vector plus immediate)
01 ST1H (vector plus immediate)
10 ST1W (vector plus immediate)
11 UNALLOCATED

SVE Memory - Contiguous Store with Immediate Offset

These instructions are under SVE encodings.

313029282726252423222120191817161514131211109876543210
1110010op0op1111
Decode fieldsInstruction details
op0op1
00 1 SVE contiguous non-temporal store (scalar plus immediate)
!= 00 1 SVE store multiple structures (scalar plus immediate)
0 SVE contiguous store (scalar plus immediate)

SVE contiguous non-temporal store (scalar plus immediate)

These instructions are under SVE Memory - Contiguous Store with Immediate Offset.

313029282726252423222120191817161514131211109876543210
1110010msz001imm4111PgRnZt
Decode fields Instruction Details
msz
00 STNT1B (scalar plus immediate, single register)
01 STNT1H (scalar plus immediate, single register)
10 STNT1W (scalar plus immediate, single register)
11 STNT1D (scalar plus immediate, single register)

SVE store multiple structures (scalar plus immediate)

These instructions are under SVE Memory - Contiguous Store with Immediate Offset.

313029282726252423222120191817161514131211109876543210
1110010msz!= 001imm4111PgRnZt
opc

The following constraints also apply to this encoding: opc != 00 && opc != 00

Decode fields Instruction Details
msz opc
00 01 ST2B (scalar plus immediate)
00 10 ST3B (scalar plus immediate)
00 11 ST4B (scalar plus immediate)
01 01 ST2H (scalar plus immediate)
01 10 ST3H (scalar plus immediate)
01 11 ST4H (scalar plus immediate)
10 01 ST2W (scalar plus immediate)
10 10 ST3W (scalar plus immediate)
10 11 ST4W (scalar plus immediate)
11 01 ST2D (scalar plus immediate)
11 10 ST3D (scalar plus immediate)
11 11 ST4D (scalar plus immediate)

SVE contiguous store (scalar plus immediate)

These instructions are under SVE Memory - Contiguous Store with Immediate Offset.

313029282726252423222120191817161514131211109876543210
1110010mszopc0imm4111PgRnZt
Decode fields Instruction Details Feature
msz opc
00 ST1B (scalar plus immediate, single register)-
01 ST1H (scalar plus immediate, single register)-
10 00 ST1W (scalar plus immediate, single register)SVE2FEAT_SVE2p1
10 01 UNALLOCATED-
10 1x ST1W (scalar plus immediate, single register)SVE-
11 0x UNALLOCATED-
11 10 ST1D (scalar plus immediate, single register)SVE2FEAT_SVE2p1
11 11 ST1D (scalar plus immediate, single register)SVE-

Data Processing -- Immediate

These instructions are under the top-level.

313029282726252423222120191817161514131211109876543210
op0100op1
Decode fieldsInstruction details
op0op1
11 111x Data-processing (1 source immediate)
00xx PC-rel. addressing
010x Add/subtract (immediate)
0110 Add/subtract (immediate, with tags)
0111 Min/max (immediate)
100x Logical (immediate)
101x Move wide (immediate)
110x Bitfield
!= 11 111x Extract

Data-processing (1 source immediate)

These instructions are under Data Processing -- Immediate.

313029282726252423222120191817161514131211109876543210
sf11100111opcimm16Rd
Decode fields Instruction Details Feature
sf opc Rd
0 UNALLOCATED-
1 0x 0xxxx UNALLOCATED-
1 0x 10xxx UNALLOCATED-
1 0x 110xx UNALLOCATED-
1 0x 1110x UNALLOCATED-
1 0x 11110 UNALLOCATED-
1 00 11111 AUTIASPPC (immediate)FEAT_PAuth_LR
1 01 11111 AUTIBSPPC (immediate)FEAT_PAuth_LR
1 1x UNALLOCATED-

PC-rel. addressing

These instructions are under Data Processing -- Immediate.

313029282726252423222120191817161514131211109876543210
opimmlo10000immhiRd
Decode fields Instruction Details
op
0 ADR
1 ADRP

Add/subtract (immediate)

These instructions are under Data Processing -- Immediate.

313029282726252423222120191817161514131211109876543210
sfopS100010shimm12RnRd
Decode fields Instruction Details
sf op S
0 0 0 ADD (immediate)32-bit
0 0 1 ADDS (immediate)32-bit
0 1 0 SUB (immediate)32-bit
0 1 1 SUBS (immediate)32-bit
1 0 0 ADD (immediate)64-bit
1 0 1 ADDS (immediate)64-bit
1 1 0 SUB (immediate)64-bit
1 1 1 SUBS (immediate)64-bit

Add/subtract (immediate, with tags)

These instructions are under Data Processing -- Immediate.

313029282726252423222120191817161514131211109876543210
sfopS1000110uimm6op3uimm4RnRd
Decode fields Instruction Details Feature
sf op S
0 UNALLOCATED-
1 1 UNALLOCATED-
1 0 0 ADDGFEAT_MTE
1 1 0 SUBGFEAT_MTE

Min/max (immediate)

These instructions are under Data Processing -- Immediate.

313029282726252423222120191817161514131211109876543210
sfopS1000111opcimm8RnRd
Decode fields Instruction Details Feature
sf op S opc
0 0 01xx UNALLOCATED-
0 0 1xxx UNALLOCATED-
0 1 UNALLOCATED-
1 UNALLOCATED-
0 0 0 0000 SMAX (immediate)32-bitFEAT_CSSC
0 0 0 0001 UMAX (immediate)32-bitFEAT_CSSC
0 0 0 0010 SMIN (immediate)32-bitFEAT_CSSC
0 0 0 0011 UMIN (immediate)32-bitFEAT_CSSC
1 0 0 0000 SMAX (immediate)64-bitFEAT_CSSC
1 0 0 0001 UMAX (immediate)64-bitFEAT_CSSC
1 0 0 0010 SMIN (immediate)64-bitFEAT_CSSC
1 0 0 0011 UMIN (immediate)64-bitFEAT_CSSC

Logical (immediate)

These instructions are under Data Processing -- Immediate.

313029282726252423222120191817161514131211109876543210
sfopc100100NimmrimmsRnRd
Decode fields Instruction Details
sf opc N
0 1 UNALLOCATED
0 00 0 AND (immediate)32-bit
0 01 0 ORR (immediate)32-bit
0 10 0 EOR (immediate)32-bit
0 11 0 ANDS (immediate)32-bit
1 00 AND (immediate)64-bit
1 01 ORR (immediate)64-bit
1 10 EOR (immediate)64-bit
1 11 ANDS (immediate)64-bit

Move wide (immediate)

These instructions are under Data Processing -- Immediate.

313029282726252423222120191817161514131211109876543210
sfopc100101hwimm16Rd
Decode fields Instruction Details
sf opc hw
01 0x UNALLOCATED
0 1x UNALLOCATED
0 00 0x MOVN32-bit
0 10 0x MOVZ32-bit
0 11 0x MOVK32-bit
1 00 MOVN64-bit
1 01 1x UNALLOCATED
1 10 MOVZ64-bit
1 11 MOVK64-bit

Bitfield

These instructions are under Data Processing -- Immediate.

313029282726252423222120191817161514131211109876543210
sfopc100110NimmrimmsRnRd
Decode fields Instruction Details
sf opc N
0 1 UNALLOCATED
0 00 0 SBFM32-bit
0 01 0 BFM32-bit
0 10 0 UBFM32-bit
0 11 0 UNALLOCATED
1 0 UNALLOCATED
1 00 1 SBFM64-bit
1 01 1 BFM64-bit
1 10 1 UBFM64-bit
1 11 1 UNALLOCATED

Extract

These instructions are under Data Processing -- Immediate.

313029282726252423222120191817161514131211109876543210
sf!= 11100111No0RmimmsRnRd
op21

The following constraints also apply to this encoding: op21 != 11

Decode fields Instruction Details
sf op21 N o0 imms
00 1 UNALLOCATED
01 UNALLOCATED
1x UNALLOCATED
0 00 0 0 0xxxxx EXTR32-bit
0 00 0 0 1xxxxx UNALLOCATED
0 00 1 0 UNALLOCATED
1 00 0 0 UNALLOCATED
1 00 1 0 EXTR64-bit

Branches, Exception Generating and System instructions

These instructions are under the top-level.

313029282726252423222120191817161514131211109876543210
op0101op1op2
Decode fieldsInstruction details
op0op1op2
010 00xxxxxxxxxxxx Conditional branch (immediate)
010 01xxxxxxxxxxxx Miscellaneous branch (immediate)
110 00xxxxxxxxxxxx Exception generation
110 01000000110001 System instructions with register argument
110 01000000110010 11111 Hints
110 01000000110010 != 11111 UNALLOCATED
110 01000000110011 Barriers
110 0100000xxx0100 PSTATE
110 0100100xxxxxxx System with result
110 0100x01xxxxxxx System instructions
110 0100x1xxxxxxxx System register move
110 0101x01xxxxxxx System pair instructions
110 0101x1xxxxxxxx System register pair move
110 1xxxxxxxxxxxxx Unconditional branch (register)
x00 Unconditional branch (immediate)
x01 0xxxxxxxxxxxxx Compare and branch (immediate)
x01 1xxxxxxxxxxxxx Test and branch (immediate)
x11 UNALLOCATED

Conditional branch (immediate)

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
01010100imm19o0cond
Decode fields Instruction Details Feature
o0
0 B.cond-
1 BC.condFEAT_HBC

Miscellaneous branch (immediate)

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
01010101opcimm16op2
Decode fields Instruction Details Feature
opc op2
00x 0xxxx UNALLOCATED-
00x 10xxx UNALLOCATED-
00x 110xx UNALLOCATED-
00x 1110x UNALLOCATED-
00x 11110 UNALLOCATED-
000 11111 RETAASPPC, RETABSPPC (immediate)RETAASPPCFEAT_PAuth_LR
001 11111 RETAASPPC, RETABSPPC (immediate)RETABSPPCFEAT_PAuth_LR
01x UNALLOCATED-
1xx UNALLOCATED-

Exception generation

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
11010100opcimm16op2LL
Decode fields Instruction Details Feature
opc op2 LL
001 UNALLOCATED-
01x UNALLOCATED-
1xx UNALLOCATED-
x11 000 01 UNALLOCATED-
x11 000 1x UNALLOCATED-
000 000 00 UNALLOCATED-
000 000 01 SVC-
000 000 10 HVC-
000 000 11 SMC-
001 000 00 BRK-
001 000 01 UNALLOCATED-
001 000 1x UNALLOCATED-
010 000 00 HLT-
010 000 01 UNALLOCATED-
010 000 1x UNALLOCATED-
011 000 00 TCANCELFEAT_TME
1x0 000 UNALLOCATED-
1x1 000 00 UNALLOCATED-
101 000 01 DCPS1-
101 000 10 DCPS2-
101 000 11 DCPS3-

System instructions with register argument

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
11010101000000110001CRmop2Rt
Decode fields Instruction Details Feature
CRm op2
0000 000 WFETFEAT_WFxT
0000 001 WFITFEAT_WFxT
0000 01x UNALLOCATED-
0000 1xx UNALLOCATED-
0001 UNALLOCATED-
001x UNALLOCATED-
01xx UNALLOCATED-
1xxx UNALLOCATED-

Hints

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
11010101000000110010CRmop211111
Decode fields Instruction Details Feature
CRm op2
HINT-
0000 000 NOP-
0000 001 YIELD-
0000 010 WFE-
0000 011 WFI-
0000 100 SEV-
0000 101 SEVL-
0000 110 DGHFEAT_DGH
0000 111 XPACD, XPACI, XPACLRIFEAT_PAuth
0001 000 PACIA, PACIA1716, PACIASP, PACIAZ, PACIZAPACIA1716FEAT_PAuth
0001 010 PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZBPACIB1716FEAT_PAuth
0001 100 AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZAAUTIA1716FEAT_PAuth
0001 110 AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZBAUTIB1716FEAT_PAuth
0010 000 ESBFEAT_RAS
0010 001 PSBFEAT_SPE
0010 010 TSBFEAT_TRF
0010 011 GCSBFEAT_GCS
0010 100 CSDB-
0010 110 CLRBHBFEAT_CLRBHB
0011 000 PACIA, PACIA1716, PACIASP, PACIAZ, PACIZAPACIAZFEAT_PAuth
0011 001 PACIA, PACIA1716, PACIASP, PACIAZ, PACIZAPACIASPFEAT_PAuth
0011 010 PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZBPACIBZFEAT_PAuth
0011 011 PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZBPACIBSPFEAT_PAuth
0011 100 AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZAAUTIAZFEAT_PAuth
0011 101 AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZAAUTIASPFEAT_PAuth
0011 110 AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZBAUTIBZFEAT_PAuth
0011 111 AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZBAUTIBSPFEAT_PAuth
0100 xx0 BTIFEAT_BTI
0100 111 PACMFEAT_PAuth_LR
0101 000 CHKFEATFEAT_CHK

Barriers

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
11010101000000110011CRmop2Rt
Decode fields Instruction Details Feature
CRm op2 Rt
0xxxx UNALLOCATED-
10xxx UNALLOCATED-
110xx UNALLOCATED-
1110x UNALLOCATED-
11110 UNALLOCATED-
010 11111 CLREX-
100 11111 DSBMemory barrier-
101 11111 DMB-
110 11111 ISB-
111 11111 SBFEAT_SB
xxx1 011 11111 UNALLOCATED-
xx0x 00x 11111 UNALLOCATED-
xx1x 000 11111 UNALLOCATED-
xx10 001 11111 DSBMemory nXS barrierFEAT_XS
xx10 011 11111 UNALLOCATED-
xx11 001 11111 UNALLOCATED-
0000 011 11111 TCOMMITFEAT_TME
0100 011 11111 UNALLOCATED-
1x00 011 11111 UNALLOCATED-

PSTATE

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
1101010100000op10100CRmop2Rt
Decode fields Instruction Details Feature
op1 op2 Rt
0xxxx UNALLOCATED-
10xxx UNALLOCATED-
110xx UNALLOCATED-
1110x UNALLOCATED-
11110 UNALLOCATED-
11111 MSR (immediate)-
000 000 11111 CFINVFEAT_FlagM
000 001 11111 XAFLAGFEAT_FlagM2
000 010 11111 AXFLAGFEAT_FlagM2

System with result

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
1101010100100op1CRnCRmop2Rt
Decode fields Instruction Details Feature
op1 CRn CRm op2
00x UNALLOCATED-
010 UNALLOCATED-
011 000x UNALLOCATED-
011 0010 UNALLOCATED-
011 0011 000x 00x UNALLOCATED-
011 0011 000x 010 UNALLOCATED-
011 0011 000x 1xx UNALLOCATED-
011 0011 0000 011 TSTARTFEAT_TME
011 0011 0001 011 TTESTFEAT_TME
011 0011 001x UNALLOCATED-
011 0011 01xx UNALLOCATED-
011 0011 1xxx UNALLOCATED-
011 01xx UNALLOCATED-
011 1xxx UNALLOCATED-
1xx UNALLOCATED-

System instructions

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
1101010100L01op1CRnCRmop2Rt
Decode fields Instruction Details
L
0 SYS
1 SYSL

System register move

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
1101010100L1o0op1CRnCRmop2Rt
Decode fields Instruction Details
L
0 MSR (register)
1 MRS

System pair instructions

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
1101010101L01op1CRnCRmop2Rt
Decode fields Instruction Details Feature
L
0 SYSPFEAT_SYSINSTR128
1 UNALLOCATED-

System register pair move

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
1101010101L1o0op1CRnCRmop2Rt
Decode fields Instruction Details Feature
L
0 MSRRFEAT_SYSREG128
1 MRRSFEAT_SYSREG128

Unconditional branch (register)

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
1101011opcop2op3Rnop4
Decode fields Instruction Details Feature
opc op2 op3 Rn op4
!= 11111 UNALLOCATED-
0000 11111 000000 != 00000 UNALLOCATED-
0000 11111 000000 00000 BR-
0000 11111 000001 UNALLOCATED-
0000 11111 000010 != 11111 UNALLOCATED-
0000 11111 000010 11111 BRAA, BRAAZ, BRAB, BRABZKey A, zero modifierFEAT_PAuth
0000 11111 000011 != 11111 UNALLOCATED-
0000 11111 000011 11111 BRAA, BRAAZ, BRAB, BRABZKey B, zero modifierFEAT_PAuth
0000 11111 0001xx UNALLOCATED-
0000 11111 001xxx UNALLOCATED-
0000 11111 01xxxx UNALLOCATED-
0000 11111 1xxxxx UNALLOCATED-
0001 11111 000000 != 00000 UNALLOCATED-
0001 11111 000000 00000 BLR-
0001 11111 000001 UNALLOCATED-
0001 11111 000010 != 11111 UNALLOCATED-
0001 11111 000010 11111 BLRAA, BLRAAZ, BLRAB, BLRABZKey A, zero modifierFEAT_PAuth
0001 11111 000011 != 11111 UNALLOCATED-
0001 11111 000011 11111 BLRAA, BLRAAZ, BLRAB, BLRABZKey B, zero modifierFEAT_PAuth
0001 11111 0001xx UNALLOCATED-
0001 11111 001xxx UNALLOCATED-
0001 11111 01xxxx UNALLOCATED-
0001 11111 1xxxxx UNALLOCATED-
0010 11111 000000 != 00000 UNALLOCATED-
0010 11111 000000 00000 RET-
0010 11111 000001 UNALLOCATED-
0010 11111 000010 != 11111 != 11111 UNALLOCATED-
0010 11111 000010 != 11111 11111 UNALLOCATED-
0010 11111 000010 11111 != 11111 UNALLOCATED-
0010 11111 000010 11111 11111 RETAA, RETABRETAAFEAT_PAuth
0010 11111 000010 11111 != 11111 RETAASPPC, RETABSPPC (register)RETAASPPCFEAT_PAuth_LR
0010 11111 000011 != 11111 != 11111 UNALLOCATED-
0010 11111 000011 != 11111 11111 UNALLOCATED-
0010 11111 000011 11111 != 11111 UNALLOCATED-
0010 11111 000011 11111 11111 RETAA, RETABRETABFEAT_PAuth
0010 11111 000011 11111 != 11111 RETAASPPC, RETABSPPC (register)RETABSPPCFEAT_PAuth_LR
0010 11111 0001xx UNALLOCATED-
0010 11111 001xxx UNALLOCATED-
0010 11111 01xxxx UNALLOCATED-
0010 11111 1xxxxx UNALLOCATED-
0011 11111 UNALLOCATED-
0100 11111 000000 != 11111 UNALLOCATED-
0100 11111 000000 11111 != 00000 UNALLOCATED-
0100 11111 000000 11111 00000 ERET-
0100 11111 000001 UNALLOCATED-
0100 11111 000010 != 11111 != 11111 UNALLOCATED-
0100 11111 000010 != 11111 11111 UNALLOCATED-
0100 11111 000010 11111 != 11111 UNALLOCATED-
0100 11111 000010 11111 11111 ERETAA, ERETABERETAAFEAT_PAuth
0100 11111 000011 != 11111 != 11111 UNALLOCATED-
0100 11111 000011 != 11111 11111 UNALLOCATED-
0100 11111 000011 11111 != 11111 UNALLOCATED-
0100 11111 000011 11111 11111 ERETAA, ERETABERETABFEAT_PAuth
0100 11111 0001xx UNALLOCATED-
0100 11111 001xxx UNALLOCATED-
0100 11111 01xxxx UNALLOCATED-
0100 11111 1xxxxx UNALLOCATED-
0101 11111 != 000000 UNALLOCATED-
0101 11111 000000 != 11111 UNALLOCATED-
0101 11111 000000 11111 != 00000 UNALLOCATED-
0101 11111 000000 11111 00000 DRPS-
011x 11111 UNALLOCATED-
1000 11111 00000x UNALLOCATED-
1000 11111 000010 BRAA, BRAAZ, BRAB, BRABZKey A, register modifierFEAT_PAuth
1000 11111 000011 BRAA, BRAAZ, BRAB, BRABZKey B, register modifierFEAT_PAuth
1000 11111 0001xx UNALLOCATED-
1000 11111 001xxx UNALLOCATED-
1000 11111 01xxxx UNALLOCATED-
1000 11111 1xxxxx UNALLOCATED-
1001 11111 00000x UNALLOCATED-
1001 11111 000010 BLRAA, BLRAAZ, BLRAB, BLRABZKey A, register modifierFEAT_PAuth
1001 11111 000011 BLRAA, BLRAAZ, BLRAB, BLRABZKey B, register modifierFEAT_PAuth
1001 11111 0001xx UNALLOCATED-
1001 11111 001xxx UNALLOCATED-
1001 11111 01xxxx UNALLOCATED-
1001 11111 1xxxxx UNALLOCATED-
101x 11111 UNALLOCATED-
11xx 11111 UNALLOCATED-

Unconditional branch (immediate)

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
op00101imm26
Decode fields Instruction Details
op
0 B
1 BL

Compare and branch (immediate)

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
sf011010opimm19Rt
Decode fields Instruction Details
sf op
0 0 CBZ32-bit
0 1 CBNZ32-bit
1 0 CBZ64-bit
1 1 CBNZ64-bit

Test and branch (immediate)

These instructions are under Branches, Exception Generating and System instructions.

313029282726252423222120191817161514131211109876543210
b5011011opb40imm14Rt
Decode fields Instruction Details
op
0 TBZ
1 TBNZ

Data Processing -- Register

These instructions are under the top-level.

313029282726252423222120191817161514131211109876543210
op0op1101op2op3
Decode fieldsInstruction details
op0op1op2op3
0 1 0110 Data-processing (2 source)
1 1 0110 Data-processing (1 source)
0 0xxx Logical (shifted register)
0 1xx0 Add/subtract (shifted register)
0 1xx1 Add/subtract (extended register)
1 0000 000000 Add/subtract (with carry)
1 0000 001xxx Add/subtract (checked pointer)
1 0000 011xxx UNALLOCATED
1 0000 100000 UNALLOCATED
1 0000 1x1xxx UNALLOCATED
1 0000 x00001 Rotate right into flags
1 0000 x0010x UNALLOCATED
1 0000 x10x0x UNALLOCATED
1 0000 xx0010 Evaluate into flags
1 0000 xx0011 UNALLOCATED
1 0000 xx011x UNALLOCATED
1 0010 xxxx0x Conditional compare (register)
1 0010 xxxx1x Conditional compare (immediate)
1 0100 Conditional select
1 0xx1 UNALLOCATED
1 1xxx Data-processing (3 source)

Data-processing (2 source)

These instructions are under Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sf0S11010110RmopcodeRnRd
Decode fields Instruction Details Feature
sf S opcode
1xxxxx UNALLOCATED-
0 00011x UNALLOCATED-
0 0 0x11xx UNALLOCATED-
0 0 000x0x UNALLOCATED-
0 0 000010 UDIV32-bit-
0 0 000011 SDIV32-bit-
0 0 001000 LSLV32-bit-
0 0 001001 LSRV32-bit-
0 0 001010 ASRV32-bit-
0 0 001011 RORV32-bit-
0 0 010x11 UNALLOCATED-
0 0 010000 CRC32B, CRC32H, CRC32W, CRC32XCRC32BFEAT_CRC32
0 0 010001 CRC32B, CRC32H, CRC32W, CRC32XCRC32HFEAT_CRC32
0 0 010010 CRC32B, CRC32H, CRC32W, CRC32XCRC32WFEAT_CRC32
0 0 010100 CRC32CB, CRC32CH, CRC32CW, CRC32CXCRC32CBFEAT_CRC32
0 0 010101 CRC32CB, CRC32CH, CRC32CW, CRC32CXCRC32CHFEAT_CRC32
0 0 010110 CRC32CB, CRC32CH, CRC32CW, CRC32CXCRC32CWFEAT_CRC32
0 0 011000 SMAX (register)32-bitFEAT_CSSC
0 0 011001 UMAX (register)32-bitFEAT_CSSC
0 0 011010 SMIN (register)32-bitFEAT_CSSC
0 0 011011 UMIN (register)32-bitFEAT_CSSC
0 1 0xxxxx UNALLOCATED-
1 000001 UNALLOCATED-
1 01000x UNALLOCATED-
1 0 000000 SUBPFEAT_MTE
1 0 000010 UDIV64-bit-
1 0 000011 SDIV64-bit-
1 0 000100 IRGFEAT_MTE
1 0 000101 GMIFEAT_MTE
1 0 001000 LSLV64-bit-
1 0 001001 LSRV64-bit-
1 0 001010 ASRV64-bit-
1 0 001011 RORV64-bit-
1 0 001100 PACGAFEAT_PAuth
1 0 001101 UNALLOCATED-
1 0 00111x UNALLOCATED-
1 0 010x10 UNALLOCATED-
1 0 010011 CRC32B, CRC32H, CRC32W, CRC32XCRC32XFEAT_CRC32
1 0 01010x UNALLOCATED-
1 0 010111 CRC32CB, CRC32CH, CRC32CW, CRC32CXCRC32CXFEAT_CRC32
1 0 011000 SMAX (register)64-bitFEAT_CSSC
1 0 011001 UMAX (register)64-bitFEAT_CSSC
1 0 011010 SMIN (register)64-bitFEAT_CSSC
1 0 011011 UMIN (register)64-bitFEAT_CSSC
1 0 0111xx UNALLOCATED-
1 1 0x001x UNALLOCATED-
1 1 0x01xx UNALLOCATED-
1 1 0x1xxx UNALLOCATED-
1 1 000000 SUBPSFEAT_MTE

Data-processing (1 source)

These instructions are under Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sf1S11010110opcode2opcodeRnRd
Decode fields Instruction Details Feature
sf S opcode2 opcode Rn Rd
0 00000 001001 UNALLOCATED-
0 00000 00101x UNALLOCATED-
0 00000 0011xx UNALLOCATED-
0 00000 01xxxx UNALLOCATED-
0 00000 1xxxxx UNALLOCATED-
0 0001x UNALLOCATED-
0 001xx UNALLOCATED-
0 01xxx UNALLOCATED-
0 1xxxx UNALLOCATED-
1 UNALLOCATED-
0 0 00000 000000 RBIT32-bit-
0 0 00000 000001 REV1632-bit-
0 0 00000 000010 REV32-bit-
0 0 00000 000011 UNALLOCATED-
0 0 00000 000100 CLZ32-bit-
0 0 00000 000101 CLS32-bit-
0 0 00000 000110 CTZ32-bitFEAT_CSSC
0 0 00000 000111 CNT32-bitFEAT_CSSC
0 0 00000 001000 ABS32-bitFEAT_CSSC
0 0 00001 UNALLOCATED-
1 0 00000 000000 RBIT64-bit-
1 0 00000 000001 REV1664-bit-
1 0 00000 000010 REV32-
1 0 00000 000011 REV64-bit-
1 0 00000 000100 CLZ64-bit-
1 0 00000 000101 CLS64-bit-
1 0 00000 000110 CTZ64-bitFEAT_CSSC
1 0 00000 000111 CNT64-bitFEAT_CSSC
1 0 00000 001000 ABS64-bitFEAT_CSSC
1 0 00001 000000 PACIA, PACIA1716, PACIASP, PACIAZ, PACIZAPACIAFEAT_PAuth
1 0 00001 000001 PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZBPACIBFEAT_PAuth
1 0 00001 000010 PACDA, PACDZAPACDAFEAT_PAuth
1 0 00001 000011 PACDB, PACDZBPACDBFEAT_PAuth
1 0 00001 000100 AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZAAUTIAFEAT_PAuth
1 0 00001 000101 AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZBAUTIBFEAT_PAuth
1 0 00001 000110 AUTDA, AUTDZAAUTDAFEAT_PAuth
1 0 00001 000111 AUTDB, AUTDZBAUTDBFEAT_PAuth
1 0 00001 001000 11111 PACIA, PACIA1716, PACIASP, PACIAZ, PACIZAPACIZAFEAT_PAuth
1 0 00001 001001 11111 PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZBPACIZBFEAT_PAuth
1 0 00001 001010 11111 PACDA, PACDZAPACDZAFEAT_PAuth
1 0 00001 001011 11111 PACDB, PACDZBPACDZBFEAT_PAuth
1 0 00001 001100 11111 AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZAAUTIZAFEAT_PAuth
1 0 00001 001101 11111 AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZBAUTIZBFEAT_PAuth
1 0 00001 001110 11111 AUTDA, AUTDZAAUTDZAFEAT_PAuth
1 0 00001 001111 11111 AUTDB, AUTDZBAUTDZBFEAT_PAuth
1 0 00001 010000 11111 XPACD, XPACI, XPACLRIXPACIFEAT_PAuth
1 0 00001 010001 11111 XPACD, XPACI, XPACLRIXPACDFEAT_PAuth
1 0 00001 01001x UNALLOCATED-
1 0 00001 0101xx UNALLOCATED-
1 0 00001 011xxx UNALLOCATED-
1 0 00001 100000 11111 11110 PACNBIASPPCFEAT_PAuth_LR
1 0 00001 100001 11111 11110 PACNBIBSPPCFEAT_PAuth_LR
1 0 00001 100010 11111 11110 PACIA171615FEAT_PAuth_LR
1 0 00001 100011 11111 11110 PACIB171615FEAT_PAuth_LR
1 0 00001 100100 11110 AUTIASPPC (register)FEAT_PAuth_LR
1 0 00001 100101 11110 AUTIBSPPC (register)FEAT_PAuth_LR
1 0 00001 101000 11111 11110 PACIASPPCFEAT_PAuth_LR
1 0 00001 101001 11111 11110 PACIBSPPCFEAT_PAuth_LR
1 0 00001 101110 11111 11110 AUTIA171615FEAT_PAuth_LR
1 0 00001 101111 11111 11110 AUTIB171615FEAT_PAuth_LR

Logical (shifted register)

These instructions are under Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfopc01010shiftNRmimm6RnRd
Decode fields Instruction Details
sf opc N
0 00 0 AND (shifted register)32-bit
0 00 1 BIC (shifted register)32-bit
0 01 0 ORR (shifted register)32-bit
0 01 1 ORN (shifted register)32-bit
0 10 0 EOR (shifted register)32-bit
0 10 1 EON (shifted register)32-bit
0 11 0 ANDS (shifted register)32-bit
0 11 1 BICS (shifted register)32-bit
1 00 0 AND (shifted register)64-bit
1 00 1 BIC (shifted register)64-bit
1 01 0 ORR (shifted register)64-bit
1 01 1 ORN (shifted register)64-bit
1 10 0 EOR (shifted register)64-bit
1 10 1 EON (shifted register)64-bit
1 11 0 ANDS (shifted register)64-bit
1 11 1 BICS (shifted register)64-bit

Add/subtract (shifted register)

These instructions are under Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfopS01011shift0Rmimm6RnRd
Decode fields Instruction Details
sf op S
0 0 0 ADD (shifted register)32-bit
0 0 1 ADDS (shifted register)32-bit
0 1 0 SUB (shifted register)32-bit
0 1 1 SUBS (shifted register)32-bit
1 0 0 ADD (shifted register)64-bit
1 0 1 ADDS (shifted register)64-bit
1 1 0 SUB (shifted register)64-bit
1 1 1 SUBS (shifted register)64-bit

Add/subtract (extended register)

These instructions are under Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfopS01011opt1Rmoptionimm3RnRd
Decode fields Instruction Details
sf op S opt
01 UNALLOCATED
1x UNALLOCATED
0 0 0 00 ADD (extended register)32-bit
0 0 1 00 ADDS (extended register)32-bit
0 1 0 00 SUB (extended register)32-bit
0 1 1 00 SUBS (extended register)32-bit
1 0 0 00 ADD (extended register)64-bit
1 0 1 00 ADDS (extended register)64-bit
1 1 0 00 SUB (extended register)64-bit
1 1 1 00 SUBS (extended register)64-bit

Add/subtract (with carry)

These instructions are under Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfopS11010000Rm000000RnRd
Decode fields Instruction Details
sf op S
0 0 0 ADC32-bit
0 0 1 ADCS32-bit
0 1 0 SBC32-bit
0 1 1 SBCS32-bit
1 0 0 ADC64-bit
1 0 1 ADCS64-bit
1 1 0 SBC64-bit
1 1 1 SBCS64-bit

Add/subtract (checked pointer)

These instructions are under Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfopS11010000Rm001imm3RnRd
Decode fields Instruction Details Feature
sf op S
0 UNALLOCATED-
1 1 UNALLOCATED-
1 0 0 ADDPTFEAT_CPA
1 1 0 SUBPTFEAT_CPA

Rotate right into flags

These instructions are under Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfopS11010000imm600001Rno2mask
Decode fields Instruction Details Feature
sf op S o2
0 UNALLOCATED-
1 0 0 UNALLOCATED-
1 0 1 0 RMIFFEAT_FlagM
1 0 1 1 UNALLOCATED-
1 1 UNALLOCATED-

Evaluate into flags

These instructions are under Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfopS11010000opcode2sz0010Rno3mask
Decode fields Instruction Details Feature
sf op S opcode2 sz o3 mask
0 0 0 UNALLOCATED-
0 0 1 000000 0 0xxx UNALLOCATED-
0 0 1 000000 0 10xx UNALLOCATED-
0 0 1 000000 0 1100 UNALLOCATED-
0 0 1 000000 0 111x UNALLOCATED-
0 0 1 000000 1 UNALLOCATED-
0 0 1 000000 0 0 1101 SETF8, SETF16SETF8FEAT_FlagM
0 0 1 000000 1 0 1101 SETF8, SETF16SETF16FEAT_FlagM
0 0 1 000001 UNALLOCATED-
0 0 1 00001x UNALLOCATED-
0 0 1 0001xx UNALLOCATED-
0 0 1 001xxx UNALLOCATED-
0 0 1 01xxxx UNALLOCATED-
0 0 1 1xxxxx UNALLOCATED-
0 1 UNALLOCATED-
1 UNALLOCATED-

Conditional compare (register)

These instructions are under Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfopS11010010Rmcond0o2Rno3nzcv
Decode fields Instruction Details
sf op S o2 o3
0 UNALLOCATED
1 0 1 UNALLOCATED
1 1 UNALLOCATED
0 0 1 0 0 CCMN (register)32-bit
0 1 1 0 0 CCMP (register)32-bit
1 0 1 0 0 CCMN (register)64-bit
1 1 1 0 0 CCMP (register)64-bit

Conditional compare (immediate)

These instructions are under Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfopS11010010imm5cond1o2Rno3nzcv
Decode fields Instruction Details
sf op S o2 o3
0 UNALLOCATED
1 0 1 UNALLOCATED
1 1 UNALLOCATED
0 0 1 0 0 CCMN (immediate)32-bit
0 1 1 0 0 CCMP (immediate)32-bit
1 0 1 0 0 CCMN (immediate)64-bit
1 1 1 0 0 CCMP (immediate)64-bit

Conditional select

These instructions are under Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfopS11010100Rmcondop2RnRd
Decode fields Instruction Details
sf op S op2
0 1x UNALLOCATED
1 UNALLOCATED
0 0 0 00 CSEL32-bit
0 0 0 01 CSINC32-bit
0 1 0 00 CSINV32-bit
0 1 0 01 CSNEG32-bit
1 0 0 00 CSEL64-bit
1 0 0 01 CSINC64-bit
1 1 0 00 CSINV64-bit
1 1 0 01 CSNEG64-bit

Data-processing (3 source)

These instructions are under Data Processing -- Register.

313029282726252423222120191817161514131211109876543210
sfop5411011op31Rmo0RaRnRd
Decode fields Instruction Details Feature
sf op54 op31 o0
00 100 UNALLOCATED-
01 UNALLOCATED-
1x UNALLOCATED-
0 00 x01 UNALLOCATED-
0 00 x1x UNALLOCATED-
0 00 000 0 MADD32-bit-
0 00 000 1 MSUB32-bit-
1 00 x10 1 UNALLOCATED-
1 00 000 0 MADD64-bit-
1 00 000 1 MSUB64-bit-
1 00 001 0 SMADDL-
1 00 001 1 SMSUBL-
1 00 010 0 SMULH-
1 00 011 0 MADDPTFEAT_CPA
1 00 011 1 MSUBPTFEAT_CPA
1 00 101 0 UMADDL-
1 00 101 1 UMSUBL-
1 00 110 0 UMULH-
1 00 111 UNALLOCATED-

Data Processing -- Scalar Floating-Point and Advanced SIMD

These instructions are under the top-level.

313029282726252423222120191817161514131211109876543210
op0111op1op2op3
Decode fieldsInstruction detailsFeature
op0op1op2op3
0000 0x x101 00xxxxx10 UNALLOCATED-
0010 0x x101 00xxxxx10 UNALLOCATED-
0100 0x x101 00xxxxx10 Cryptographic AES-
0101 0x x0xx xxx0xxx00 Cryptographic three-register SHA-
0101 0x x0xx xxx0xxx10 UNALLOCATED-
0101 0x x101 00xxxxx10 Cryptographic two-register SHA-
0110 0x x101 00xxxxx10 UNALLOCATED-
0111 0x x0xx xxx0xxxx0 UNALLOCATED-
0111 0x x101 00xxxxx10 UNALLOCATED-
01x1 00 00xx xxx0xxxx1 Advanced SIMD scalar copy-
01x1 01 00xx xxx0xxxx1 UNALLOCATED-
01x1 0x 0111 00xxxxx10 UNALLOCATED-
01x1 0x 10xx xxx00xxx1 Advanced SIMD scalar three same FP16-
01x1 0x 10xx xxx01xxx1 UNALLOCATED-
01x1 0x 1111 00xxxxx10 Advanced SIMD scalar two-register miscellaneous FP16-
01x1 0x x0xx xxx1xxxx0 UNALLOCATED-
01x1 0x x0xx xxx1xxxx1 Advanced SIMD scalar three same extra-
01x1 0x x100 00xxxxx10 Advanced SIMD scalar two-register miscellaneous-
01x1 0x x110 00xxxxx10 Advanced SIMD scalar pairwise-
01x1 0x x1xx 01xxxxx10 UNALLOCATED-
01x1 0x x1xx 1xxxxxx10 UNALLOCATED-
01x1 0x x1xx xxxxxxx00 Advanced SIMD scalar three different-
01x1 0x x1xx xxxxxxxx1 Advanced SIMD scalar three same-
01x1 10 xxxxxxxx1 Advanced SIMD scalar shift by immediate-
01x1 11 xxxxxxxx1 UNALLOCATED-
01x1 1x xxxxxxxx0 Advanced SIMD scalar x indexed element-
0x00 0x x0xx xxx0xxx00 Advanced SIMD table lookup-
0x00 0x x0xx xxx0xxx10 Advanced SIMD permute-
0x10 0x x0xx xxx0xxxx0 Advanced SIMD extract-
0xx0 00 00xx xxx0xxxx1 Advanced SIMD copy-
0xx0 01 00xx xxx0xxxx1 UNALLOCATED-
0xx0 0x 0111 00xxxxx10 UNALLOCATED-
0xx0 0x 10xx xxx00xxx1 Advanced SIMD three same (FP16)-
0xx0 0x 10xx xxx01xxx1 UNALLOCATED-
0xx0 0x 1111 00xxxxx10 Advanced SIMD two-register miscellaneous (FP16)-
0xx0 0x x0xx xxx1xxxx0 UNALLOCATED-
0xx0 0x x0xx xxx1xxxx1 Advanced SIMD three-register extension-
0xx0 0x x100 00xxxxx10 Advanced SIMD two-register miscellaneous-
0xx0 0x x110 00xxxxx10 Advanced SIMD across lanes-
0xx0 0x x1xx 01xxxxx10 UNALLOCATED-
0xx0 0x x1xx 1xxxxxx10 UNALLOCATED-
0xx0 0x x1xx xxxxxxx00 Advanced SIMD three different-
0xx0 0x x1xx xxxxxxxx1 Advanced SIMD three same-
0xx0 10 0000 xxxxxxxx1 Advanced SIMD modified immediate-
0xx0 10 != 0000 xxxxxxxx1 Advanced SIMD shift by immediate-
0xx0 11 xxxxxxxx1 UNALLOCATED-
0xx0 1x xxxxxxxx0 Advanced SIMD vector x indexed element-
1100 00 10xx xxx10xxxx Cryptographic three-register, imm2-
1100 00 11xx xxx1x00xx Cryptographic three-register SHA 512-
1100 00 xxx0xxxxx Cryptographic four-register-
1100 01 00xx XARFEAT_SHA3
1100 01 1000 0001000xx Cryptographic two-register SHA 512-
1xx0 1x UNALLOCATED-
x0x1 0x x0xx Conversion between floating-point and fixed-point-
x0x1 0x x1xx xxx000000 Conversion between floating-point and integer-
x0x1 0x x1xx xxxx10000 Floating-point data-processing (1 source)-
x0x1 0x x1xx xxxxx1000 Floating-point compare-
x0x1 0x x1xx xxxxxx100 Floating-point immediate-
x0x1 0x x1xx xxxxxxx01 Floating-point conditional compare-
x0x1 0x x1xx xxxxxxx10 Floating-point data-processing (2 source)-
x0x1 0x x1xx xxxxxxx11 Floating-point conditional select-
x0x1 1x Floating-point data-processing (3 source)-

Cryptographic AES

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01001110size10100opcode10RnRd
Decode fields Instruction Details Feature
size opcode
00 000xx UNALLOCATED-
00 00100 AESEFEAT_AES
00 00101 AESDFEAT_AES
00 00110 AESMCFEAT_AES
00 00111 AESIMCFEAT_AES
00 01xxx UNALLOCATED-
00 1xxxx UNALLOCATED-
01 UNALLOCATED-
1x UNALLOCATED-

Cryptographic three-register SHA

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01011110size0Rm0opcode00RnRd
Decode fields Instruction Details Feature
size opcode
00 000 SHA1CFEAT_SHA1
00 001 SHA1PFEAT_SHA1
00 010 SHA1MFEAT_SHA1
00 011 SHA1SU0FEAT_SHA1
00 100 SHA256HFEAT_SHA256
00 101 SHA256H2FEAT_SHA256
00 110 SHA256SU1FEAT_SHA256
00 111 UNALLOCATED-
01 UNALLOCATED-
1x UNALLOCATED-

Cryptographic two-register SHA

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01011110size10100opcode10RnRd
Decode fields Instruction Details Feature
size opcode
00 00000 SHA1HFEAT_SHA1
00 00001 SHA1SU1FEAT_SHA1
00 00010 SHA256SU0FEAT_SHA256
00 00011 UNALLOCATED-
00 001xx UNALLOCATED-
00 01xxx UNALLOCATED-
00 1xxxx UNALLOCATED-
01 UNALLOCATED-
1x UNALLOCATED-

Advanced SIMD scalar copy

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01op11110000imm50imm41RnRd
Decode fields Instruction Details
op imm4
0 0000 DUP (element)
0 0001 UNALLOCATED
0 001x UNALLOCATED
0 01xx UNALLOCATED
0 1xxx UNALLOCATED
1 UNALLOCATED

Advanced SIMD scalar three same FP16

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01U11110a10Rm00opcode1RnRd
Decode fields Instruction Details Feature
U a opcode
00x UNALLOCATED-
1 011 UNALLOCATED-
0 x10 UNALLOCATED-
0 0 011 FMULXFEAT_FP16
0 0 100 FCMEQ (register)FEAT_FP16
0 0 101 UNALLOCATED-
0 0 111 FRECPSFEAT_FP16
0 1 10x UNALLOCATED-
0 1 111 FRSQRTSFEAT_FP16
1 11x UNALLOCATED-
1 0 01x UNALLOCATED-
1 0 100 FCMGE (register)FEAT_FP16
1 0 101 FACGEFEAT_FP16
1 1 010 FABDFEAT_FP16
1 1 100 FCMGT (register)FEAT_FP16
1 1 101 FACGTFEAT_FP16

Advanced SIMD scalar two-register miscellaneous FP16

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01U11110a111100opcode10RnRd
Decode fields Instruction Details Feature
U a opcode
x0xxx UNALLOCATED-
1100x UNALLOCATED-
0 01xxx UNALLOCATED-
1 010xx UNALLOCATED-
1 11100 UNALLOCATED-
0 0 11010 FCVTNS (vector)FEAT_FP16
0 0 11011 FCVTMS (vector)FEAT_FP16
0 0 11100 FCVTAS (vector)FEAT_FP16
0 0 11101 SCVTF (vector, integer)FEAT_FP16
0 0 1111x UNALLOCATED-
0 1 01100 FCMGT (zero)FEAT_FP16
0 1 01101 FCMEQ (zero)FEAT_FP16
0 1 01110 FCMLT (zero)FEAT_FP16
0 1 01111 UNALLOCATED-
0 1 11010 FCVTPS (vector)FEAT_FP16
0 1 11011 FCVTZS (vector, integer)FEAT_FP16
0 1 11101 FRECPEFEAT_FP16
0 1 11110 UNALLOCATED-
0 1 11111 FRECPXFEAT_FP16
1 1111x UNALLOCATED-
1 0 11010 FCVTNU (vector)FEAT_FP16
1 0 11011 FCVTMU (vector)FEAT_FP16
1 0 11100 FCVTAU (vector)FEAT_FP16
1 0 11101 UCVTF (vector, integer)FEAT_FP16
1 1 01100 FCMGE (zero)FEAT_FP16
1 1 01101 FCMLE (zero)FEAT_FP16
1 1 0111x UNALLOCATED-
1 1 11010 FCVTPU (vector)FEAT_FP16
1 1 11011 FCVTZU (vector, integer)FEAT_FP16
1 1 11101 FRSQRTEFEAT_FP16

Advanced SIMD scalar three same extra

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01U11110size0Rm1opcode1RnRd
Decode fields Instruction Details Feature
U opcode
0 UNALLOCATED-
1 0000 SQRDMLAH (vector)FEAT_RDM
1 0001 SQRDMLSH (vector)FEAT_RDM
1 001x UNALLOCATED-
1 01xx UNALLOCATED-
1 1xxx UNALLOCATED-

Advanced SIMD scalar two-register miscellaneous

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01U11110size10000opcode10RnRd
Decode fields Instruction Details
U size opcode
00x0x UNALLOCATED
1x000 UNALLOCATED
10xx1 UNALLOCATED
11001 UNALLOCATED
0x 01xxx UNALLOCATED
0x 1111x UNALLOCATED
1x 01111 UNALLOCATED
1x 11100 UNALLOCATED
10 010x1 UNALLOCATED
10 01000 UNALLOCATED
0 x0x10 UNALLOCATED
0 00011 SUQADD
0 00111 SQABS
0 10100 SQXTN, SQXTN2
0 0x 11010 FCVTNS (vector)
0 0x 11011 FCVTMS (vector)
0 0x 11100 FCVTAS (vector)
0 0x 11101 SCVTF (vector, integer)
0 1x 01100 FCMGT (zero)
0 1x 01101 FCMEQ (zero)
0 1x 01110 FCMLT (zero)
0 1x 11010 FCVTPS (vector)
0 1x 11011 FCVTZS (vector, integer)
0 1x 11101 FRECPE
0 1x 11110 UNALLOCATED
0 1x 11111 FRECPX
0 10 01010 UNALLOCATED
0 11 01000 CMGT (zero)
0 11 01001 CMEQ (zero)
0 11 01010 CMLT (zero)
0 11 01011 ABS
1 00x10 UNALLOCATED
1 00011 USQADD
1 00111 SQNEG
1 10010 SQXTUN, SQXTUN2
1 10100 UQXTN, UQXTN2
1 0x 11010 FCVTNU (vector)
1 0x 11011 FCVTMU (vector)
1 0x 11100 FCVTAU (vector)
1 0x 11101 UCVTF (vector, integer)
1 00 10110 UNALLOCATED
1 01 10110 FCVTXN, FCVTXN2
1 1x 01x10 UNALLOCATED
1 1x 01100 FCMGE (zero)
1 1x 01101 FCMLE (zero)
1 1x 1x110 UNALLOCATED
1 1x 11010 FCVTPU (vector)
1 1x 11011 FCVTZU (vector, integer)
1 1x 11101 FRSQRTE
1 1x 11111 UNALLOCATED
1 11 01000 CMGE (zero)
1 11 01001 CMLE (zero)
1 11 01011 NEG (vector)

Advanced SIMD scalar pairwise

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01U11110size11000opcode10RnRd
Decode fields Instruction Details Feature
U size opcode
x0xxx UNALLOCATED-
01110 UNALLOCATED-
111xx UNALLOCATED-
10 01101 UNALLOCATED-
0 x1 011x1 UNALLOCATED-
0 x1 01100 UNALLOCATED-
0 0x x10xx UNALLOCATED-
0 00 01100 FMAXNMP (scalar)Half-precisionFEAT_FP16
0 00 01101 FADDP (scalar)Half-precisionFEAT_FP16
0 00 01111 FMAXP (scalar)Half-precisionFEAT_FP16
0 10 x10xx UNALLOCATED-
0 10 01100 FMINNMP (scalar)Half-precisionFEAT_FP16
0 10 01111 FMINP (scalar)Half-precisionFEAT_FP16
0 11 x1010 UNALLOCATED-
0 11 010x1 UNALLOCATED-
0 11 01000 UNALLOCATED-
0 11 1100x UNALLOCATED-
0 11 11011 ADDP (scalar)-
1 x10xx UNALLOCATED-
1 0x 01100 FMAXNMP (scalar)Single-precision and double-precision-
1 0x 01101 FADDP (scalar)Single-precision and double-precision-
1 0x 01111 FMAXP (scalar)Single-precision and double-precision-
1 1x 01100 FMINNMP (scalar)Single-precision and double-precision-
1 1x 01111 FMINP (scalar)Single-precision and double-precision-
1 11 01101 UNALLOCATED-

Advanced SIMD scalar three different

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01U11110size1Rmopcode00RnRd
Decode fields Instruction Details
U opcode
0 0xxx UNALLOCATED
0 1xx0 UNALLOCATED
0 1001 SQDMLAL, SQDMLAL2 (vector)
0 1011 SQDMLSL, SQDMLSL2 (vector)
0 1101 SQDMULL, SQDMULL2 (vector)
0 1111 UNALLOCATED
1 UNALLOCATED

Advanced SIMD scalar three same

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01U11110size1Rmopcode1RnRd
Decode fields Instruction Details
U size opcode
x0011 UNALLOCATED
011x1 UNALLOCATED
1010x UNALLOCATED
11001 UNALLOCATED
11110 UNALLOCATED
x0 0x1x0 UNALLOCATED
x1 00100 UNALLOCATED
x1 011x0 UNALLOCATED
0x xx0x0 UNALLOCATED
0x 00111 UNALLOCATED
0x 10001 UNALLOCATED
01 00110 UNALLOCATED
1x 10010 UNALLOCATED
1x 11000 UNALLOCATED
10 0x0x0 UNALLOCATED
10 00111 UNALLOCATED
10 1000x UNALLOCATED
11 00000 UNALLOCATED
11 00010 UNALLOCATED
0 00001 SQADD
0 00101 SQSUB
0 01001 SQSHL (register)
0 01011 SQRSHL
0 10110 SQDMULH (vector)
0 10111 UNALLOCATED
0 0x 11011 FMULX
0 0x 11100 FCMEQ (register)
0 0x 11101 UNALLOCATED
0 0x 11111 FRECPS
0 1x 1101x UNALLOCATED
0 1x 1110x UNALLOCATED
0 1x 11111 FRSQRTS
0 11 00110 CMGT (register)
0 11 00111 CMGE (register)
0 11 01000 SSHL
0 11 01010 SRSHL
0 11 10000 ADD (vector)
0 11 10001 CMTST
1 00001 UQADD
1 00101 UQSUB
1 01001 UQSHL (register)
1 01011 UQRSHL
1 1x111 UNALLOCATED
1 10110 SQRDMULH (vector)
1 11011 UNALLOCATED
1 0x 11100 FCMGE (register)
1 0x 11101 FACGE
1 1x 11010 FABD
1 1x 11100 FCMGT (register)
1 1x 11101 FACGT
1 11 00110 CMHI (register)
1 11 00111 CMHS (register)
1 11 01000 USHL
1 11 01010 URSHL
1 11 10000 SUB (vector)
1 11 10001 CMEQ (register)

Advanced SIMD scalar shift by immediate

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01U111110immhimmbopcode1RnRd
Decode fields Instruction Details
U immh opcode
0xxx1 UNALLOCATED
101xx UNALLOCATED
110xx UNALLOCATED
11101 UNALLOCATED
xxx1 11110 UNALLOCATED
xx10 11110 UNALLOCATED
x100 11110 UNALLOCATED
0xxx 00xx0 UNALLOCATED
0xxx 010x0 UNALLOCATED
0000 x1110 UNALLOCATED
0000 1001x UNALLOCATED
0000 11100 UNALLOCATED
0000 11111 UNALLOCATED
1000 11110 UNALLOCATED
0 1xxx 00000 SSHR
0 1xxx 00010 SSRA
0 1xxx 00100 SRSHR
0 1xxx 00110 SRSRA
0 1xxx 01010 SHL
0 01100 UNALLOCATED
0 != 0000 01110 SQSHL (immediate)
0 1000x UNALLOCATED
0 != 0000 10010 SQSHRN, SQSHRN2
0 != 0000 10011 SQRSHRN, SQRSHRN2
0 != 0000 11100 SCVTF (vector, fixed-point)
0 != 0000 11111 FCVTZS (vector, fixed-point)
0 1xxx 01000 UNALLOCATED
1 1xxx 00000 USHR
1 1xxx 00010 USRA
1 1xxx 00100 URSHR
1 1xxx 00110 URSRA
1 1xxx 01000 SRI
1 1xxx 01010 SLI
1 != 0000 01100 SQSHLU
1 != 0000 01110 UQSHL (immediate)
1 != 0000 10000 SQSHRUN, SQSHRUN2
1 != 0000 10001 SQRSHRUN, SQRSHRUN2
1 != 0000 10010 UQSHRN, UQSHRN2
1 != 0000 10011 UQRSHRN, UQRSHRN2
1 != 0000 11100 UCVTF (vector, fixed-point)
1 != 0000 11111 FCVTZU (vector, fixed-point)
1 0000 01100 UNALLOCATED
1 0000 1000x UNALLOCATED

Advanced SIMD scalar x indexed element

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
01U11111sizeLMRmopcodeH0RnRd
Decode fields Instruction Details Feature
U size opcode
01 1001 UNALLOCATED-
0 0xx0 UNALLOCATED-
0 0011 SQDMLAL, SQDMLAL2 (by element)-
0 0111 SQDMLSL, SQDMLSL2 (by element)-
0 10x0 UNALLOCATED-
0 1011 SQDMULL, SQDMULL2 (by element)-
0 1100 SQDMULH (by element)-
0 1101 SQRDMULH (by element)-
0 111x UNALLOCATED-
0 00 0001 FMLA (by element)Scalar, half-precisionFEAT_FP16
0 00 0101 FMLS (by element)Scalar, half-precisionFEAT_FP16
0 00 1001 FMUL (by element)Scalar, half-precisionFEAT_FP16
0 01 0x01 UNALLOCATED-
0 1x 0001 FMLA (by element)Scalar, single-precision and double-precision-
0 1x 0101 FMLS (by element)Scalar, single-precision and double-precision-
0 1x 1001 FMUL (by element)Scalar, single-precision and double-precision-
1 0xxx UNALLOCATED-
1 1xx0 UNALLOCATED-
1 1011 UNALLOCATED-
1 1101 SQRDMLAH (by element)FEAT_RDM
1 1111 SQRDMLSH (by element)FEAT_RDM
1 00 1001 FMULX (by element)Scalar, half-precisionFEAT_FP16
1 1x 1001 FMULX (by element)Scalar, single-precision and double-precision-

Advanced SIMD table lookup

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0Q001110op20Rm0lenop00RnRd
Decode fields Instruction Details Feature
Q op2 len op
00 00 0 TBLSingle register table-
00 00 1 TBXSingle register table-
00 01 0 TBLTwo register table-
00 01 1 TBXTwo register table-
00 10 0 TBLThree register table-
00 10 1 TBXThree register table-
00 11 0 TBLFour register table-
00 11 1 TBXFour register table-
0 01 UNALLOCATED-
0 1x UNALLOCATED-
1 01 1 LUTI4HalfwordFEAT_LUT
1 01 x0 0 UNALLOCATED-
1 01 x1 0 LUTI4ByteFEAT_LUT
1 10 0 UNALLOCATED-
1 10 1 LUTI2ByteFEAT_LUT
1 11 LUTI2HalfwordFEAT_LUT

Advanced SIMD permute

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0Q001110size0Rm0opcode10RnRd
Decode fields Instruction Details
opcode
x00 UNALLOCATED
001 UZP1
010 TRN1
011 ZIP1
101 UZP2
110 TRN2
111 ZIP2

Advanced SIMD extract

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0Q101110op20Rm0imm40RnRd
Decode fields Instruction Details
op2
00 EXT
01 UNALLOCATED
1x UNALLOCATED

Advanced SIMD copy

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0Qop01110000imm50imm41RnRd
Decode fields Instruction Details
Q op imm5 imm4
0 0000 DUP (element)
0 0001 DUP (general)
0 01x0 UNALLOCATED
0 1xxx UNALLOCATED
0 0 001x UNALLOCATED
0 0 0101 SMOV32-bit
0 0 0111 UMOV32-bit
0 1 UNALLOCATED
1 0 0010 UNALLOCATED
1 0 0011 INS (general)
1 0 0101 SMOV64-bit
1 0 x0xxx 0111 UNALLOCATED
1 0 x1000 0111 UMOV64-bit
1 0 x1001 0111 UNALLOCATED
1 0 x101x 0111 UNALLOCATED
1 0 x11xx 0111 UNALLOCATED
1 1 INS (element)

Advanced SIMD three same (FP16)

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0QU01110a10Rm00opcode1RnRd
Decode fields Instruction Details Feature
U a opcode
0 0 000 FMAXNM (vector)FEAT_FP16
0 0 001 FMLA (vector)FEAT_FP16
0 0 010 FADD (vector)FEAT_FP16
0 0 011 FMULXFEAT_FP16
0 0 100 FCMEQ (register)FEAT_FP16
0 0 101 UNALLOCATED-
0 0 110 FMAX (vector)FEAT_FP16
0 0 111 FRECPSFEAT_FP16
0 1 000 FMINNM (vector)FEAT_FP16
0 1 001 FMLS (vector)FEAT_FP16
0 1 010 FSUB (vector)FEAT_FP16
0 1 011 FAMAXFEAT_FAMINMAX
0 1 10x UNALLOCATED-
0 1 110 FMIN (vector)FEAT_FP16
0 1 111 FRSQRTSFEAT_FP16
1 001 UNALLOCATED-
1 0 000 FMAXNMP (vector)FEAT_FP16
1 0 010 FADDP (vector)FEAT_FP16
1 0 011 FMUL (vector)FEAT_FP16
1 0 100 FCMGE (register)FEAT_FP16
1 0 101 FACGEFEAT_FP16
1 0 110 FMAXP (vector)FEAT_FP16
1 0 111 FDIV (vector)FEAT_FP16
1 1 000 FMINNMP (vector)FEAT_FP16
1 1 010 FABDFEAT_FP16
1 1 011 FAMINFEAT_FAMINMAX
1 1 100 FCMGT (register)FEAT_FP16
1 1 101 FACGTFEAT_FP16
1 1 110 FMINP (vector)FEAT_FP16
1 1 111 FSCALEFEAT_FP8

Advanced SIMD two-register miscellaneous (FP16)

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0QU01110a111100opcode10RnRd
Decode fields Instruction Details Feature
U a opcode
x0xxx UNALLOCATED-
0 01xxx UNALLOCATED-
0 1111x UNALLOCATED-
1 010xx UNALLOCATED-
1 11100 UNALLOCATED-
0 0 11000 FRINTN (vector)FEAT_FP16
0 0 11001 FRINTM (vector)FEAT_FP16
0 0 11010 FCVTNS (vector)FEAT_FP16
0 0 11011 FCVTMS (vector)FEAT_FP16
0 0 11100 FCVTAS (vector)FEAT_FP16
0 0 11101 SCVTF (vector, integer)FEAT_FP16
0 1 01100 FCMGT (zero)FEAT_FP16
0 1 01101 FCMEQ (zero)FEAT_FP16
0 1 01110 FCMLT (zero)FEAT_FP16
0 1 01111 FABS (vector)FEAT_FP16
0 1 11000 FRINTP (vector)FEAT_FP16
0 1 11001 FRINTZ (vector)FEAT_FP16
0 1 11010 FCVTPS (vector)FEAT_FP16
0 1 11011 FCVTZS (vector, integer)FEAT_FP16
0 1 11101 FRECPEFEAT_FP16
0 1 1111x UNALLOCATED-
1 0 11000 FRINTA (vector)FEAT_FP16
1 0 11001 FRINTX (vector)FEAT_FP16
1 0 11010 FCVTNU (vector)FEAT_FP16
1 0 11011 FCVTMU (vector)FEAT_FP16
1 0 11100 FCVTAU (vector)FEAT_FP16
1 0 11101 UCVTF (vector, integer)FEAT_FP16
1 1 01100 FCMGE (zero)FEAT_FP16
1 1 01101 FCMLE (zero)FEAT_FP16
1 1 01110 UNALLOCATED-
1 1 01111 FNEG (vector)FEAT_FP16
1 1 11000 UNALLOCATED-
1 1 11001 FRINTI (vector)FEAT_FP16
1 1 11010 FCVTPU (vector)FEAT_FP16
1 1 11011 FCVTZU (vector, integer)FEAT_FP16
1 1 11101 FRSQRTEFEAT_FP16
1 1 11110 UNALLOCATED-
1 1 11111 FSQRT (vector)FEAT_FP16

Advanced SIMD three-register extension

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0QU01110size0Rm1opcode1RnRd
Decode fields Instruction Details Feature
Q U size opcode
0 0010 SDOT (vector)FEAT_DotProd
0 0x x011 UNALLOCATED-
0 0x 000x UNALLOCATED-
0 0x 1001 UNALLOCATED-
0 0x 1010 UNALLOCATED-
0 0x 1100 UNALLOCATED-
0 00 1110 FCVTN, FCVTN2 (single-precision to 8-bit floating-point)FEAT_FP8
0 00 1111 FDOT (8-bit floating-point to single-precision, vector)FEAT_FP8DOT4
0 01 1110 FCVTN (half-precision to 8-bit floating-point)FEAT_FP8
0 01 1111 FDOT (8-bit floating-point to half-precision, vector)FEAT_FP8DOT2
0 1x 000x UNALLOCATED-
0 10 0011 USDOT (vector)FEAT_I8MM
0 10 1xx0 UNALLOCATED-
0 10 1x11 UNALLOCATED-
0 10 1001 UNALLOCATED-
0 11 0011 UNALLOCATED-
0 11 1xx0 UNALLOCATED-
0 11 1001 UNALLOCATED-
0 11 1011 UNALLOCATED-
1 0000 SQRDMLAH (vector)FEAT_RDM
1 0001 SQRDMLSH (vector)FEAT_RDM
1 0010 UDOT (vector)FEAT_DotProd
1 0011 UNALLOCATED-
1 10xx FCMLAFEAT_FCMA
1 11x0 FCADDFEAT_FCMA
1 x0 1111 UNALLOCATED-
1 01 1111 BFDOT (vector)FEAT_BF16
1 11 1111 BFMLALB, BFMLALT (vector)FEAT_BF16
0 01xx UNALLOCATED-
0 1101 UNALLOCATED-
0 0 00 1000 FMLALLBB, FMLALLBT, FMLALLTB, FMLALLTT (vector)FMLALLBBFEAT_FP8FMA
0 0 01 1000 FMLALLBB, FMLALLBT, FMLALLTB, FMLALLTT (vector)FMLALLBTFEAT_FP8FMA
0 0 11 1111 FMLALB, FMLALT (vector)FMLALBFEAT_FP8FMA
1 0x 01xx UNALLOCATED-
1 10 011x UNALLOCATED-
1 11 01xx UNALLOCATED-
1 11 1101 UNALLOCATED-
1 0 0x 1101 UNALLOCATED-
1 0 00 1000 FMLALLBB, FMLALLBT, FMLALLTB, FMLALLTT (vector)FMLALLTBFEAT_FP8FMA
1 0 01 1000 FMLALLBB, FMLALLBT, FMLALLTB, FMLALLTT (vector)FMLALLTTFEAT_FP8FMA
1 0 10 0100 SMMLA (vector)FEAT_I8MM
1 0 10 0101 USMMLA (vector)FEAT_I8MM
1 0 10 1101 UNALLOCATED-
1 0 11 1111 FMLALB, FMLALT (vector)FMLALTFEAT_FP8FMA
1 1 x0 1101 UNALLOCATED-
1 1 01 1101 BFMMLAFEAT_BF16
1 1 10 0100 UMMLA (vector)FEAT_I8MM
1 1 10 0101 UNALLOCATED-

Advanced SIMD two-register miscellaneous

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0QU01110size10000opcode10RnRd
Decode fields Instruction Details Feature
U size opcode
1000x UNALLOCATED-
10101 UNALLOCATED-
0x 011xx UNALLOCATED-
0 00000 REV64-
0 00001 REV16 (vector)-
0 00010 SADDLP-
0 00011 SUQADD-
0 00100 CLS (vector)-
0 00101 CNT-
0 00110 SADALP-
0 00111 SQABS-
0 01000 CMGT (zero)-
0 01001 CMEQ (zero)-
0 01010 CMLT (zero)-
0 01011 ABS-
0 10010 XTN, XTN2-
0 10100 SQXTN, SQXTN2-
0 0x 10011 UNALLOCATED-
0 0x 10110 FCVTN, FCVTN2 (double to single-precision, single to half-precision)-
0 0x 10111 FCVTL, FCVTL2-
0 0x 11000 FRINTN (vector)-
0 0x 11001 FRINTM (vector)-
0 0x 11010 FCVTNS (vector)-
0 0x 11011 FCVTMS (vector)-
0 0x 11100 FCVTAS (vector)-
0 0x 11101 SCVTF (vector, integer)-
0 0x 11110 FRINT32Z (vector)FEAT_FRINTTS
0 0x 11111 FRINT64Z (vector)FEAT_FRINTTS
0 1x 01100 FCMGT (zero)-
0 1x 01101 FCMEQ (zero)-
0 1x 01110 FCMLT (zero)-
0 1x 01111 FABS (vector)-
0 1x 10x11 UNALLOCATED-
0 1x 11000 FRINTP (vector)-
0 1x 11001 FRINTZ (vector)-
0 1x 11010 FCVTPS (vector)-
0 1x 11011 FCVTZS (vector, integer)-
0 1x 11100 URECPE-
0 1x 11101 FRECPE-
0 10 10110 BFCVTN, BFCVTN2FEAT_BF16
0 10 1111x UNALLOCATED-
0 11 1x110 UNALLOCATED-
0 11 11111 UNALLOCATED-
1 00000 REV32 (vector)-
1 00010 UADDLP-
1 00011 USQADD-
1 00100 CLZ (vector)-
1 00110 UADALP-
1 00111 SQNEG-
1 01000 CMGE (zero)-
1 01001 CMLE (zero)-
1 01010 UNALLOCATED-
1 01011 NEG (vector)-
1 10010 SQXTUN, SQXTUN2-
1 10011 SHLL, SHLL2-
1 10100 UQXTN, UQXTN2-
1 0x 00001 UNALLOCATED-
1 0x 11000 FRINTA (vector)-
1 0x 11001 FRINTX (vector)-
1 0x 11010 FCVTNU (vector)-
1 0x 11011 FCVTMU (vector)-
1 0x 11100 FCVTAU (vector)-
1 0x 11101 UCVTF (vector, integer)-
1 0x 11110 FRINT32X (vector)FEAT_FRINTTS
1 0x 11111 FRINT64X (vector)FEAT_FRINTTS
1 00 00101 NOT-
1 00 10110 UNALLOCATED-
1 00 10111 F1CVTL, F1CVTL2, F2CVTL, F2CVTL2F1CVTL{2}FEAT_FP8
1 01 00101 RBIT (vector)-
1 01 10110 FCVTXN, FCVTXN2-
1 01 10111 F1CVTL, F1CVTL2, F2CVTL, F2CVTL2F2CVTL{2}FEAT_FP8
1 1x 00x01 UNALLOCATED-
1 1x 01100 FCMGE (zero)-
1 1x 01101 FCMLE (zero)-
1 1x 01110 UNALLOCATED-
1 1x 01111 FNEG (vector)-
1 1x 1x110 UNALLOCATED-
1 1x 11000 UNALLOCATED-
1 1x 11001 FRINTI (vector)-
1 1x 11010 FCVTPU (vector)-
1 1x 11011 FCVTZU (vector, integer)-
1 1x 11100 URSQRTE-
1 1x 11101 FRSQRTE-
1 1x 11111 FSQRT (vector)-
1 10 10111 BF1CVTL, BF1CVTL2, BF2CVTL, BF2CVTL2BF1CVTL{2}FEAT_FP8
1 11 10111 BF1CVTL, BF1CVTL2, BF2CVTL, BF2CVTL2BF2CVTL{2}FEAT_FP8

Advanced SIMD across lanes

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0QU01110size11000opcode10RnRd
Decode fields Instruction Details Feature
Q U size opcode
x100x UNALLOCATED-
000x0 UNALLOCATED-
00001 UNALLOCATED-
01011 UNALLOCATED-
100xx UNALLOCATED-
x0 001xx UNALLOCATED-
x0 01101 UNALLOCATED-
x0 101xx UNALLOCATED-
x0 111xx UNALLOCATED-
x1 xx1xx UNALLOCATED-
0 00011 SADDLV-
0 01010 SMAXV-
0 11010 SMINV-
0 11011 ADDV-
0 x0 01110 UNALLOCATED-
0 00 01100 FMAXNMVHalf-precisionFEAT_FP16
0 00 01111 FMAXVHalf-precisionFEAT_FP16
0 10 01100 FMINNMVHalf-precisionFEAT_FP16
0 10 01111 FMINVHalf-precisionFEAT_FP16
1 00011 UADDLV-
1 01010 UMAXV-
1 11010 UMINV-
1 11011 UNALLOCATED-
1 1 00 01100 FMAXNMVSingle-precision-
1 1 00 01111 FMAXVSingle-precision-
1 1 10 01100 FMINNMVSingle-precision-
1 1 10 01111 FMINVSingle-precision-
0 1 x0 011x0 UNALLOCATED-
0 1 x0 01111 UNALLOCATED-
1 1 x0 01110 UNALLOCATED-

Advanced SIMD three different

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0QU01110size1Rmopcode00RnRd
Decode fields Instruction Details
U opcode
0 0000 SADDL, SADDL2
0 0001 SADDW, SADDW2
0 0010 SSUBL, SSUBL2
0 0011 SSUBW, SSUBW2
0 0100 ADDHN, ADDHN2
0 0101 SABAL, SABAL2
0 0110 SUBHN, SUBHN2
0 0111 SABDL, SABDL2
0 1000 SMLAL, SMLAL2 (vector)
0 1001 SQDMLAL, SQDMLAL2 (vector)
0 1010 SMLSL, SMLSL2 (vector)
0 1011 SQDMLSL, SQDMLSL2 (vector)
0 1100 SMULL, SMULL2 (vector)
0 1101 SQDMULL, SQDMULL2 (vector)
0 1110 PMULL, PMULL2
0 1111 UNALLOCATED
1 0000 UADDL, UADDL2
1 0001 UADDW, UADDW2
1 0010 USUBL, USUBL2
1 0011 USUBW, USUBW2
1 0100 RADDHN, RADDHN2
1 0101 UABAL, UABAL2
1 0110 RSUBHN, RSUBHN2
1 0111 UABDL, UABDL2
1 1xx1 UNALLOCATED
1 1000 UMLAL, UMLAL2 (vector)
1 1010 UMLSL, UMLSL2 (vector)
1 1100 UMULL, UMULL2 (vector)
1 1110 UNALLOCATED

Advanced SIMD three same

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0QU01110size1Rmopcode1RnRd
Decode fields Instruction Details Feature
U size opcode
0 00000 SHADD-
0 00001 SQADD-
0 00010 SRHADD-
0 00100 SHSUB-
0 00101 SQSUB-
0 00110 CMGT (register)-
0 00111 CMGE (register)-
0 01000 SSHL-
0 01001 SQSHL (register)-
0 01010 SRSHL-
0 01011 SQRSHL-
0 01100 SMAX-
0 01101 SMIN-
0 01110 SABD-
0 01111 SABA-
0 10000 ADD (vector)-
0 10001 CMTST-
0 10010 MLA (vector)-
0 10011 MUL (vector)-
0 10100 SMAXP-
0 10101 SMINP-
0 10110 SQDMULH (vector)-
0 10111 ADDP (vector)-
0 1x 11011 FAMAXFEAT_FAMINMAX
0 x1 11101 UNALLOCATED-
0 0x 11000 FMAXNM (vector)-
0 0x 11001 FMLA (vector)-
0 0x 11010 FADD (vector)-
0 0x 11011 FMULX-
0 0x 11100 FCMEQ (register)-
0 0x 11110 FMAX (vector)-
0 0x 11111 FRECPS-
0 00 00011 AND (vector)-
0 00 11101 FMLAL, FMLAL2 (vector)FMLALFEAT_FHM
0 01 00011 BIC (vector, register)-
0 1x 11000 FMINNM (vector)-
0 1x 11001 FMLS (vector)-
0 1x 11010 FSUB (vector)-
0 1x 11100 UNALLOCATED-
0 1x 11110 FMIN (vector)-
0 1x 11111 FRSQRTS-
0 10 00011 ORR (vector, register)-
0 10 11101 FMLSL, FMLSL2 (vector)FMLSLFEAT_FHM
0 11 00011 ORN (vector)-
1 00000 UHADD-
1 00001 UQADD-
1 00010 URHADD-
1 00100 UHSUB-
1 00101 UQSUB-
1 00110 CMHI (register)-
1 00111 CMHS (register)-
1 01000 USHL-
1 01001 UQSHL (register)-
1 01010 URSHL-
1 01011 UQRSHL-
1 01100 UMAX-
1 01101 UMIN-
1 01110 UABD-
1 01111 UABA-
1 10000 SUB (vector)-
1 10001 CMEQ (register)-
1 10010 MLS (vector)-
1 10011 PMUL-
1 10100 UMAXP-
1 10101 UMINP-
1 10110 SQRDMULH (vector)-
1 10111 UNALLOCATED-
1 1x 11011 FAMINFEAT_FAMINMAX
1 1x 11111 FSCALEFEAT_FP8
1 x1 11001 UNALLOCATED-
1 0x 11000 FMAXNMP (vector)-
1 0x 11010 FADDP (vector)-
1 0x 11011 FMUL (vector)-
1 0x 11100 FCMGE (register)-
1 0x 11101 FACGE-
1 0x 11110 FMAXP (vector)-
1 0x 11111 FDIV (vector)-
1 00 00011 EOR (vector)-
1 00 11001 FMLAL, FMLAL2 (vector)FMLAL2FEAT_FHM
1 01 00011 BSL-
1 1x 11000 FMINNMP (vector)-
1 1x 11010 FABD-
1 1x 11100 FCMGT (register)-
1 1x 11101 FACGT-
1 1x 11110 FMINP (vector)-
1 10 00011 BIT-
1 10 11001 FMLSL, FMLSL2 (vector)FMLSL2FEAT_FHM
1 11 00011 BIF-

Advanced SIMD modified immediate

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0Qop0111100000abccmodeo21defghRd
Decode fields Instruction Details Feature
Q op cmode o2
0 0xxx 1 UNALLOCATED-
0 0xx0 0 MOVI32-bit shifted immediate-
0 0xx1 0 ORR (vector, immediate)32-bit-
0 10xx 1 UNALLOCATED-
0 10x0 0 MOVI16-bit shifted immediate-
0 10x1 0 ORR (vector, immediate)16-bit-
0 110x 0 MOVI32-bit shifting ones-
0 110x 1 UNALLOCATED-
0 1110 0 MOVI8-bit-
0 1110 1 UNALLOCATED-
0 1111 0 FMOV (vector, immediate)Single-precision-
0 1111 1 FMOV (vector, immediate)Half-precisionFEAT_FP16
1 1 UNALLOCATED-
1 0xx0 0 MVNI32-bit shifted immediate-
1 0xx1 0 BIC (vector, immediate)32-bit-
1 10x0 0 MVNI16-bit shifted immediate-
1 10x1 0 BIC (vector, immediate)16-bit-
1 110x 0 MVNI32-bit shifting ones-
0 1 1110 0 MOVI64-bit scalar-
0 1 1111 0 UNALLOCATED-
1 1 1110 0 MOVI64-bit vector-
1 1 1111 0 FMOV (vector, immediate)Double-precision-

Advanced SIMD shift by immediate

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0QU011110!= 0000immbopcode1RnRd
immh

The following constraints also apply to this encoding: immh != 0000

Decode fields Instruction Details
U immh opcode
0xxx1 UNALLOCATED
101x1 UNALLOCATED
110xx UNALLOCATED
11101 UNALLOCATED
xxx1 1x110 UNALLOCATED
xx10 1x110 UNALLOCATED
x100 1x110 UNALLOCATED
0000 x0xx0 UNALLOCATED
0000 01x10 UNALLOCATED
0000 100x1 UNALLOCATED
0000 111x0 UNALLOCATED
0000 11111 UNALLOCATED
1000 1x110 UNALLOCATED
0 != 0000 00000 SSHR
0 != 0000 00010 SSRA
0 != 0000 00100 SRSHR
0 != 0000 00110 SRSRA
0 01x00 UNALLOCATED
0 != 0000 01010 SHL
0 != 0000 01110 SQSHL (immediate)
0 != 0000 10000 SHRN, SHRN2
0 != 0000 10001 RSHRN, RSHRN2
0 != 0000 10010 SQSHRN, SQSHRN2
0 != 0000 10011 SQRSHRN, SQRSHRN2
0 != 0000 10100 SSHLL, SSHLL2
0 != 0000 11100 SCVTF (vector, fixed-point)
0 != 0000 11111 FCVTZS (vector, fixed-point)
1 != 0000 00000 USHR
1 != 0000 00010 USRA
1 != 0000 00100 URSHR
1 != 0000 00110 URSRA
1 != 0000 01000 SRI
1 != 0000 01010 SLI
1 != 0000 01100 SQSHLU
1 != 0000 01110 UQSHL (immediate)
1 != 0000 10000 SQSHRUN, SQSHRUN2
1 != 0000 10001 SQRSHRUN, SQRSHRUN2
1 != 0000 10010 UQSHRN, UQSHRN2
1 != 0000 10011 UQRSHRN, UQRSHRN2
1 != 0000 10100 USHLL, USHLL2
1 != 0000 11100 UCVTF (vector, fixed-point)
1 != 0000 11111 FCVTZU (vector, fixed-point)
1 0000 01x00 UNALLOCATED

Advanced SIMD vector x indexed element

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
0QU01111sizeLMRmopcodeH0RnRd
Decode fields Instruction Details Feature
Q U size opcode
01 1001 UNALLOCATED-
0 0010 SMLAL, SMLAL2 (by element)-
0 0011 SQDMLAL, SQDMLAL2 (by element)-
0 0110 SMLSL, SMLSL2 (by element)-
0 0111 SQDMLSL, SQDMLSL2 (by element)-
0 1000 MUL (by element)-
0 1010 SMULL, SMULL2 (by element)-
0 1011 SQDMULL, SQDMULL2 (by element)-
0 1100 SQDMULH (by element)-
0 1101 SQRDMULH (by element)-
0 1110 SDOT (by element)FEAT_DotProd
0 0x 0100 UNALLOCATED-
0 00 0000 FDOT (8-bit floating-point to single-precision, by element)FEAT_FP8DOT4
0 00 0001 FMLA (by element)Vector, half-precisionFEAT_FP16
0 00 0101 FMLS (by element)Vector, half-precisionFEAT_FP16
0 00 1001 FMUL (by element)Vector, half-precisionFEAT_FP16
0 00 1111 SUDOT (by element)FEAT_I8MM
0 01 0x01 UNALLOCATED-
0 01 0000 FDOT (8-bit floating-point to half-precision, by element)FEAT_FP8DOT2
0 01 1111 BFDOT (by element)FEAT_BF16
0 1x 0001 FMLA (by element)Vector, single-precision and double-precision-
0 1x 0101 FMLS (by element)Vector, single-precision and double-precision-
0 1x 1001 FMUL (by element)Vector, single-precision and double-precision-
0 10 0000 FMLAL, FMLAL2 (by element)FMLALFEAT_FHM
0 10 0100 FMLSL, FMLSL2 (by element)FMLSLFEAT_FHM
0 10 1111 USDOT (by element)FEAT_I8MM
0 11 0100 UNALLOCATED-
0 11 1111 BFMLALB, BFMLALT (by element)FEAT_BF16
1 0xx1 FCMLA (by element)FEAT_FCMA
1 0000 MLA (by element)-
1 0010 UMLAL, UMLAL2 (by element)-
1 0100 MLS (by element)-
1 0110 UMLSL, UMLSL2 (by element)-
1 1010 UMULL, UMULL2 (by element)-
1 1011 UNALLOCATED-
1 1101 SQRDMLAH (by element)FEAT_RDM
1 1110 UDOT (by element)FEAT_DotProd
1 1111 SQRDMLSH (by element)FEAT_RDM
1 0x 1100 UNALLOCATED-
1 00 1001 FMULX (by element)Vector, half-precisionFEAT_FP16
1 1x 1001 FMULX (by element)Vector, single-precision and double-precision-
1 10 1000 FMLAL, FMLAL2 (by element)FMLAL2FEAT_FHM
1 10 1100 FMLSL, FMLSL2 (by element)FMLSL2FEAT_FHM
1 11 1x00 UNALLOCATED-
0 0 11 0000 FMLALB, FMLALT (by element)FMLALBFEAT_FP8FMA
0 1 00 1000 FMLALLBB, FMLALLBT, FMLALLTB, FMLALLTT (by element)FMLALLBBFEAT_FP8FMA
0 1 01 1000 FMLALLBB, FMLALLBT, FMLALLTB, FMLALLTT (by element)FMLALLBTFEAT_FP8FMA
1 0 11 0000 FMLALB, FMLALT (by element)FMLALTFEAT_FP8FMA
1 1 00 1000 FMLALLBB, FMLALLBT, FMLALLTB, FMLALLTT (by element)FMLALLTBFEAT_FP8FMA
1 1 01 1000 FMLALLBB, FMLALLBT, FMLALLTB, FMLALLTT (by element)FMLALLTTFEAT_FP8FMA

Cryptographic three-register, imm2

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
11001110010Rm10imm2opcodeRnRd
Decode fields Instruction Details Feature
opcode
00 SM3TT1AFEAT_SM3
01 SM3TT1BFEAT_SM3
10 SM3TT2AFEAT_SM3
11 SM3TT2BFEAT_SM3

Cryptographic three-register SHA 512

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
11001110011Rm1O00opcodeRnRd
Decode fields Instruction Details Feature
O opcode
0 00 SHA512HFEAT_SHA512
0 01 SHA512H2FEAT_SHA512
0 10 SHA512SU1FEAT_SHA512
0 11 RAX1FEAT_SHA3
1 00 SM3PARTW1FEAT_SM3
1 01 SM3PARTW2FEAT_SM3
1 10 SM4EKEYFEAT_SM4
1 11 UNALLOCATED-

Cryptographic four-register

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
110011100Op0Rm0RaRnRd
Decode fields Instruction Details Feature
Op0
00 EOR3FEAT_SHA3
01 BCAXFEAT_SHA3
10 SM3SS1FEAT_SM3
11 UNALLOCATED-

Cryptographic two-register SHA 512

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
11001110110000001000opcodeRnRd
Decode fields Instruction Details Feature
opcode
00 SHA512SU0FEAT_SHA512
01 SM4EFEAT_SM4
1x UNALLOCATED-

Conversion between floating-point and fixed-point

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
sf0S11110ftype0rmodeopcodescaleRnRd
Decode fields Instruction Details Feature
sf S ftype rmode opcode
0 1xx UNALLOCATED-
0 x1 x1 01x UNALLOCATED-
0 x1 0x 00x UNALLOCATED-
0 x1 10 0xx UNALLOCATED-
0 00 x1 01x UNALLOCATED-
0 00 0x 00x UNALLOCATED-
0 00 10 0xx UNALLOCATED-
0 10 0xx UNALLOCATED-
1 UNALLOCATED-
0 0 00 00 010 SCVTF (scalar, fixed-point)32-bit to single-precision-
0 0 00 00 011 UCVTF (scalar, fixed-point)32-bit to single-precision-
0 0 00 11 000 FCVTZS (scalar, fixed-point)Single-precision to 32-bit-
0 0 00 11 001 FCVTZU (scalar, fixed-point)Single-precision to 32-bit-
0 0 01 00 010 SCVTF (scalar, fixed-point)32-bit to double-precision-
0 0 01 00 011 UCVTF (scalar, fixed-point)32-bit to double-precision-
0 0 01 11 000 FCVTZS (scalar, fixed-point)Double-precision to 32-bit-
0 0 01 11 001 FCVTZU (scalar, fixed-point)Double-precision to 32-bit-
0 0 11 00 010 SCVTF (scalar, fixed-point)32-bit to half-precisionFEAT_FP16
0 0 11 00 011 UCVTF (scalar, fixed-point)32-bit to half-precisionFEAT_FP16
0 0 11 11 000 FCVTZS (scalar, fixed-point)Half-precision to 32-bitFEAT_FP16
0 0 11 11 001 FCVTZU (scalar, fixed-point)Half-precision to 32-bitFEAT_FP16
1 0 00 00 010 SCVTF (scalar, fixed-point)64-bit to single-precision-
1 0 00 00 011 UCVTF (scalar, fixed-point)64-bit to single-precision-
1 0 00 11 000 FCVTZS (scalar, fixed-point)Single-precision to 64-bit-
1 0 00 11 001 FCVTZU (scalar, fixed-point)Single-precision to 64-bit-
1 0 01 00 010 SCVTF (scalar, fixed-point)64-bit to double-precision-
1 0 01 00 011 UCVTF (scalar, fixed-point)64-bit to double-precision-
1 0 01 11 000 FCVTZS (scalar, fixed-point)Double-precision to 64-bit-
1 0 01 11 001 FCVTZU (scalar, fixed-point)Double-precision to 64-bit-
1 0 11 00 010 SCVTF (scalar, fixed-point)64-bit to half-precisionFEAT_FP16
1 0 11 00 011 UCVTF (scalar, fixed-point)64-bit to half-precisionFEAT_FP16
1 0 11 11 000 FCVTZS (scalar, fixed-point)Half-precision to 64-bitFEAT_FP16
1 0 11 11 001 FCVTZU (scalar, fixed-point)Half-precision to 64-bitFEAT_FP16

Conversion between floating-point and integer

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
sf0S11110ftype1rmodeopcode000000RnRd
Decode fields Instruction Details Feature
sf S ftype rmode opcode
0 01 10x UNALLOCATED-
0 x1 x1 01x UNALLOCATED-
0 x1 10 01x UNALLOCATED-
0 x1 10 1xx UNALLOCATED-
0 x1 11 1x1 UNALLOCATED-
0 x1 11 100 UNALLOCATED-
0 00 x1 01x UNALLOCATED-
0 00 10 01x UNALLOCATED-
0 00 10 1xx UNALLOCATED-
0 00 11 1x1 UNALLOCATED-
0 00 11 100 UNALLOCATED-
0 10 00 UNALLOCATED-
0 10 01 0xx UNALLOCATED-
0 10 1x UNALLOCATED-
1 UNALLOCATED-
0 0 00 x1 110 UNALLOCATED-
0 0 00 00 000 FCVTNS (scalar)Single-precision to 32-bit-
0 0 00 00 001 FCVTNU (scalar)Single-precision to 32-bit-
0 0 00 00 010 SCVTF (scalar, integer)32-bit to single-precision-
0 0 00 00 011 UCVTF (scalar, integer)32-bit to single-precision-
0 0 00 00 100 FCVTAS (scalar)Single-precision to 32-bit-
0 0 00 00 101 FCVTAU (scalar)Single-precision to 32-bit-
0 0 00 00 110 FMOV (general)Single-precision to 32-bit-
0 0 00 00 111 FMOV (general)32-bit to single-precision-
0 0 00 01 000 FCVTPS (scalar)Single-precision to 32-bit-
0 0 00 01 001 FCVTPU (scalar)Single-precision to 32-bit-
0 0 00 01 111 UNALLOCATED-
0 0 00 10 000 FCVTMS (scalar)Single-precision to 32-bit-
0 0 00 10 001 FCVTMU (scalar)Single-precision to 32-bit-
0 0 00 11 000 FCVTZS (scalar, integer)Single-precision to 32-bit-
0 0 00 11 001 FCVTZU (scalar, integer)Single-precision to 32-bit-
0 0 01 0x 11x UNALLOCATED-
0 0 01 00 000 FCVTNS (scalar)Double-precision to 32-bit-
0 0 01 00 001 FCVTNU (scalar)Double-precision to 32-bit-
0 0 01 00 010 SCVTF (scalar, integer)32-bit to double-precision-
0 0 01 00 011 UCVTF (scalar, integer)32-bit to double-precision-
0 0 01 00 100 FCVTAS (scalar)Double-precision to 32-bit-
0 0 01 00 101 FCVTAU (scalar)Double-precision to 32-bit-
0 0 01 01 000 FCVTPS (scalar)Double-precision to 32-bit-
0 0 01 01 001 FCVTPU (scalar)Double-precision to 32-bit-
0 0 01 10 000 FCVTMS (scalar)Double-precision to 32-bit-
0 0 01 10 001 FCVTMU (scalar)Double-precision to 32-bit-
0 0 01 11 000 FCVTZS (scalar, integer)Double-precision to 32-bit-
0 0 01 11 001 FCVTZU (scalar, integer)Double-precision to 32-bit-
0 0 01 11 110 FJCVTZSFEAT_JSCVT
0 0 1x 01 11x UNALLOCATED-
0 0 11 00 000 FCVTNS (scalar)Half-precision to 32-bitFEAT_FP16
0 0 11 00 001 FCVTNU (scalar)Half-precision to 32-bitFEAT_FP16
0 0 11 00 010 SCVTF (scalar, integer)32-bit to half-precisionFEAT_FP16
0 0 11 00 011 UCVTF (scalar, integer)32-bit to half-precisionFEAT_FP16
0 0 11 00 100 FCVTAS (scalar)Half-precision to 32-bitFEAT_FP16
0 0 11 00 101 FCVTAU (scalar)Half-precision to 32-bitFEAT_FP16
0 0 11 00 110 FMOV (general)Half-precision to 32-bitFEAT_FP16
0 0 11 00 111 FMOV (general)32-bit to half-precisionFEAT_FP16
0 0 11 01 000 FCVTPS (scalar)Half-precision to 32-bitFEAT_FP16
0 0 11 01 001 FCVTPU (scalar)Half-precision to 32-bitFEAT_FP16
0 0 11 10 000 FCVTMS (scalar)Half-precision to 32-bitFEAT_FP16
0 0 11 10 001 FCVTMU (scalar)Half-precision to 32-bitFEAT_FP16
0 0 11 11 000 FCVTZS (scalar, integer)Half-precision to 32-bitFEAT_FP16
0 0 11 11 001 FCVTZU (scalar, integer)Half-precision to 32-bitFEAT_FP16
0 0 11 11 110 UNALLOCATED-
1 0 x1 x1 110 UNALLOCATED-
1 0 x1 01 111 UNALLOCATED-
1 0 00 0x 11x UNALLOCATED-
1 0 00 00 000 FCVTNS (scalar)Single-precision to 64-bit-
1 0 00 00 001 FCVTNU (scalar)Single-precision to 64-bit-
1 0 00 00 010 SCVTF (scalar, integer)64-bit to single-precision-
1 0 00 00 011 UCVTF (scalar, integer)64-bit to single-precision-
1 0 00 00 100 FCVTAS (scalar)Single-precision to 64-bit-
1 0 00 00 101 FCVTAU (scalar)Single-precision to 64-bit-
1 0 00 01 000 FCVTPS (scalar)Single-precision to 64-bit-
1 0 00 01 001 FCVTPU (scalar)Single-precision to 64-bit-
1 0 00 10 000 FCVTMS (scalar)Single-precision to 64-bit-
1 0 00 10 001 FCVTMU (scalar)Single-precision to 64-bit-
1 0 00 11 000 FCVTZS (scalar, integer)Single-precision to 64-bit-
1 0 00 11 001 FCVTZU (scalar, integer)Single-precision to 64-bit-
1 0 00 11 110 UNALLOCATED-
1 0 01 00 000 FCVTNS (scalar)Double-precision to 64-bit-
1 0 01 00 001 FCVTNU (scalar)Double-precision to 64-bit-
1 0 01 00 010 SCVTF (scalar, integer)64-bit to double-precision-
1 0 01 00 011 UCVTF (scalar, integer)64-bit to double-precision-
1 0 01 00 100 FCVTAS (scalar)Double-precision to 64-bit-
1 0 01 00 101 FCVTAU (scalar)Double-precision to 64-bit-
1 0 01 00 110 FMOV (general)Double-precision to 64-bit-
1 0 01 00 111 FMOV (general)64-bit to double-precision-
1 0 01 01 000 FCVTPS (scalar)Double-precision to 64-bit-
1 0 01 01 001 FCVTPU (scalar)Double-precision to 64-bit-
1 0 01 10 000 FCVTMS (scalar)Double-precision to 64-bit-
1 0 01 10 001 FCVTMU (scalar)Double-precision to 64-bit-
1 0 01 11 000 FCVTZS (scalar, integer)Double-precision to 64-bit-
1 0 01 11 001 FCVTZU (scalar, integer)Double-precision to 64-bit-
1 0 10 01 110 FMOV (general)Top half of 128-bit to 64-bit-
1 0 10 01 111 FMOV (general)64-bit to top half of 128-bit-
1 0 11 00 000 FCVTNS (scalar)Half-precision to 64-bitFEAT_FP16
1 0 11 00 001 FCVTNU (scalar)Half-precision to 64-bitFEAT_FP16
1 0 11 00 010 SCVTF (scalar, integer)64-bit to half-precisionFEAT_FP16
1 0 11 00 011 UCVTF (scalar, integer)64-bit to half-precisionFEAT_FP16
1 0 11 00 100 FCVTAS (scalar)Half-precision to 64-bitFEAT_FP16
1 0 11 00 101 FCVTAU (scalar)Half-precision to 64-bitFEAT_FP16
1 0 11 00 110 FMOV (general)Half-precision to 64-bitFEAT_FP16
1 0 11 00 111 FMOV (general)64-bit to half-precisionFEAT_FP16
1 0 11 01 000 FCVTPS (scalar)Half-precision to 64-bitFEAT_FP16
1 0 11 01 001 FCVTPU (scalar)Half-precision to 64-bitFEAT_FP16
1 0 11 10 000 FCVTMS (scalar)Half-precision to 64-bitFEAT_FP16
1 0 11 10 001 FCVTMU (scalar)Half-precision to 64-bitFEAT_FP16
1 0 11 11 000 FCVTZS (scalar, integer)Half-precision to 64-bitFEAT_FP16
1 0 11 11 001 FCVTZU (scalar, integer)Half-precision to 64-bitFEAT_FP16

Floating-point data-processing (1 source)

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
M0S11110ftype1opcode10000RnRd
Decode fields Instruction Details Feature
M S ftype opcode
0 0 1xxxxx UNALLOCATED-
0 0 x1 001101 UNALLOCATED-
0 0 0x 0101xx UNALLOCATED-
0 0 0x 011xxx UNALLOCATED-
0 0 00 000000 FMOV (register)Single-precision-
0 0 00 000001 FABS (scalar)Single-precision-
0 0 00 000010 FNEG (scalar)Single-precision-
0 0 00 000011 FSQRT (scalar)Single-precision-
0 0 00 0001x0 UNALLOCATED-
0 0 00 000101 FCVTSingle-precision to double-precision-
0 0 00 000111 FCVTSingle-precision to half-precision-
0 0 00 001000 FRINTN (scalar)Single-precision-
0 0 00 001001 FRINTP (scalar)Single-precision-
0 0 00 001010 FRINTM (scalar)Single-precision-
0 0 00 001011 FRINTZ (scalar)Single-precision-
0 0 00 001100 FRINTA (scalar)Single-precision-
0 0 00 001101 UNALLOCATED-
0 0 00 001110 FRINTX (scalar)Single-precision-
0 0 00 001111 FRINTI (scalar)Single-precision-
0 0 00 010000 FRINT32Z (scalar)Single-precisionFEAT_FRINTTS
0 0 00 010001 FRINT32X (scalar)Single-precisionFEAT_FRINTTS
0 0 00 010010 FRINT64Z (scalar)Single-precisionFEAT_FRINTTS
0 0 00 010011 FRINT64X (scalar)Single-precisionFEAT_FRINTTS
0 0 01 000000 FMOV (register)Double-precision-
0 0 01 000001 FABS (scalar)Double-precision-
0 0 01 000010 FNEG (scalar)Double-precision-
0 0 01 000011 FSQRT (scalar)Double-precision-
0 0 01 000100 FCVTDouble-precision to single-precision-
0 0 01 000101 UNALLOCATED-
0 0 01 000110 BFCVTFEAT_BF16
0 0 01 000111 FCVTDouble-precision to half-precision-
0 0 01 001000 FRINTN (scalar)Double-precision-
0 0 01 001001 FRINTP (scalar)Double-precision-
0 0 01 001010 FRINTM (scalar)Double-precision-
0 0 01 001011 FRINTZ (scalar)Double-precision-
0 0 01 001100 FRINTA (scalar)Double-precision-
0 0 01 001110 FRINTX (scalar)Double-precision-
0 0 01 001111 FRINTI (scalar)Double-precision-
0 0 01 010000 FRINT32Z (scalar)Double-precisionFEAT_FRINTTS
0 0 01 010001 FRINT32X (scalar)Double-precisionFEAT_FRINTTS
0 0 01 010010 FRINT64Z (scalar)Double-precisionFEAT_FRINTTS
0 0 01 010011 FRINT64X (scalar)Double-precisionFEAT_FRINTTS
0 0 10 0xxxxx UNALLOCATED-
0 0 11 000000 FMOV (register)Half-precisionFEAT_FP16
0 0 11 000001 FABS (scalar)Half-precisionFEAT_FP16
0 0 11 000010 FNEG (scalar)Half-precisionFEAT_FP16
0 0 11 000011 FSQRT (scalar)Half-precisionFEAT_FP16
0 0 11 000100 FCVTHalf-precision to single-precision-
0 0 11 000101 FCVTHalf-precision to double-precision-
0 0 11 00011x UNALLOCATED-
0 0 11 001000 FRINTN (scalar)Half-precisionFEAT_FP16
0 0 11 001001 FRINTP (scalar)Half-precisionFEAT_FP16
0 0 11 001010 FRINTM (scalar)Half-precisionFEAT_FP16
0 0 11 001011 FRINTZ (scalar)Half-precisionFEAT_FP16
0 0 11 001100 FRINTA (scalar)Half-precisionFEAT_FP16
0 0 11 001110 FRINTX (scalar)Half-precisionFEAT_FP16
0 0 11 001111 FRINTI (scalar)Half-precisionFEAT_FP16
0 0 11 01xxxx UNALLOCATED-
0 1 UNALLOCATED-
1 UNALLOCATED-

Floating-point compare

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
M0S11110ftype1Rmop1000Rnopcode2
Decode fields Instruction Details Feature
M S ftype op opcode2
0 0 00 xx001 UNALLOCATED-
0 0 00 xx01x UNALLOCATED-
0 0 00 xx1xx UNALLOCATED-
0 0 01 UNALLOCATED-
0 0 1x UNALLOCATED-
0 0 00 00 00000 FCMPSingle-precision-
0 0 00 00 01000 FCMPSingle-precision, zero-
0 0 00 00 10000 FCMPESingle-precision-
0 0 00 00 11000 FCMPESingle-precision, zero-
0 0 01 00 00000 FCMPDouble-precision-
0 0 01 00 01000 FCMPDouble-precision, zero-
0 0 01 00 10000 FCMPEDouble-precision-
0 0 01 00 11000 FCMPEDouble-precision, zero-
0 0 10 00 xx000 UNALLOCATED-
0 0 11 00 00000 FCMPHalf-precisionFEAT_FP16
0 0 11 00 01000 FCMPHalf-precision, zeroFEAT_FP16
0 0 11 00 10000 FCMPEHalf-precisionFEAT_FP16
0 0 11 00 11000 FCMPEHalf-precision, zeroFEAT_FP16
0 1 UNALLOCATED-
1 UNALLOCATED-

Floating-point immediate

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
M0S11110ftype1imm8100imm5Rd
Decode fields Instruction Details Feature
M S ftype imm5
0 0 00001 UNALLOCATED-
0 0 0001x UNALLOCATED-
0 0 001xx UNALLOCATED-
0 0 01xxx UNALLOCATED-
0 0 1xxxx UNALLOCATED-
0 0 00 00000 FMOV (scalar, immediate)Single-precision-
0 0 01 00000 FMOV (scalar, immediate)Double-precision-
0 0 10 00000 UNALLOCATED-
0 0 11 00000 FMOV (scalar, immediate)Half-precisionFEAT_FP16
0 1 UNALLOCATED-
1 UNALLOCATED-

Floating-point conditional compare

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
M0S11110ftype1Rmcond01Rnopnzcv
Decode fields Instruction Details Feature
M S ftype op
0 0 00 0 FCCMPSingle-precision-
0 0 00 1 FCCMPESingle-precision-
0 0 01 0 FCCMPDouble-precision-
0 0 01 1 FCCMPEDouble-precision-
0 0 10 UNALLOCATED-
0 0 11 0 FCCMPHalf-precisionFEAT_FP16
0 0 11 1 FCCMPEHalf-precisionFEAT_FP16
0 1 UNALLOCATED-
1 UNALLOCATED-

Floating-point data-processing (2 source)

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
M0S11110ftype1Rmopcode10RnRd
Decode fields Instruction Details Feature
M S ftype opcode
0 0 x1 1001 UNALLOCATED-
0 0 x1 101x UNALLOCATED-
0 0 x1 11xx UNALLOCATED-
0 0 00 0000 FMUL (scalar)Single-precision-
0 0 00 0001 FDIV (scalar)Single-precision-
0 0 00 0010 FADD (scalar)Single-precision-
0 0 00 0011 FSUB (scalar)Single-precision-
0 0 00 0100 FMAX (scalar)Single-precision-
0 0 00 0101 FMIN (scalar)Single-precision-
0 0 00 0110 FMAXNM (scalar)Single-precision-
0 0 00 0111 FMINNM (scalar)Single-precision-
0 0 00 1000 FNMUL (scalar)Single-precision-
0 0 00 1001 UNALLOCATED-
0 0 00 101x UNALLOCATED-
0 0 00 11xx UNALLOCATED-
0 0 01 0000 FMUL (scalar)Double-precision-
0 0 01 0001 FDIV (scalar)Double-precision-
0 0 01 0010 FADD (scalar)Double-precision-
0 0 01 0011 FSUB (scalar)Double-precision-
0 0 01 0100 FMAX (scalar)Double-precision-
0 0 01 0101 FMIN (scalar)Double-precision-
0 0 01 0110 FMAXNM (scalar)Double-precision-
0 0 01 0111 FMINNM (scalar)Double-precision-
0 0 01 1000 FNMUL (scalar)Double-precision-
0 0 10 UNALLOCATED-
0 0 11 0000 FMUL (scalar)Half-precisionFEAT_FP16
0 0 11 0001 FDIV (scalar)Half-precisionFEAT_FP16
0 0 11 0010 FADD (scalar)Half-precisionFEAT_FP16
0 0 11 0011 FSUB (scalar)Half-precisionFEAT_FP16
0 0 11 0100 FMAX (scalar)Half-precisionFEAT_FP16
0 0 11 0101 FMIN (scalar)Half-precisionFEAT_FP16
0 0 11 0110 FMAXNM (scalar)Half-precisionFEAT_FP16
0 0 11 0111 FMINNM (scalar)Half-precisionFEAT_FP16
0 0 11 1000 FNMUL (scalar)Half-precisionFEAT_FP16
0 1 UNALLOCATED-
1 UNALLOCATED-

Floating-point conditional select

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
M0S11110ftype1Rmcond11RnRd
Decode fields Instruction Details Feature
M S ftype
0 0 00 FCSELSingle-precision-
0 0 01 FCSELDouble-precision-
0 0 10 UNALLOCATED-
0 0 11 FCSELHalf-precisionFEAT_FP16
0 1 UNALLOCATED-
1 UNALLOCATED-

Floating-point data-processing (3 source)

These instructions are under Data Processing -- Scalar Floating-Point and Advanced SIMD.

313029282726252423222120191817161514131211109876543210
M0S11111ftypeo1Rmo0RaRnRd
Decode fields Instruction Details Feature
M S ftype o1 o0
0 0 00 0 0 FMADDSingle-precision-
0 0 00 0 1 FMSUBSingle-precision-
0 0 00 1 0 FNMADDSingle-precision-
0 0 00 1 1 FNMSUBSingle-precision-
0 0 01 0 0 FMADDDouble-precision-
0 0 01 0 1 FMSUBDouble-precision-
0 0 01 1 0 FNMADDDouble-precision-
0 0 01 1 1 FNMSUBDouble-precision-
0 0 10 UNALLOCATED-
0 0 11 0 0 FMADDHalf-precisionFEAT_FP16
0 0 11 0 1 FMSUBHalf-precisionFEAT_FP16
0 0 11 1 0 FNMADDHalf-precisionFEAT_FP16
0 0 11 1 1 FNMSUBHalf-precisionFEAT_FP16
0 1 UNALLOCATED-
1 UNALLOCATED-

Loads and Stores

These instructions are under the top-level.

313029282726252423222120191817161514131211109876543210
op01op10op2
Decode fieldsInstruction details
op0op1op2
0x00 0 00x1xxxxxxxxxxx Compare and swap pair
0x00 1 00x000000xxxxxx Advanced SIMD load/store multiple structures
0x00 1 00x000001xxxxxx UNALLOCATED
0x00 1 01x0xxxxxxxxxxx Advanced SIMD load/store multiple structures (post-indexed)
0x00 1 0xx1xxxxxxxxxxx UNALLOCATED
0x00 1 10x10001xxxxxxx UNALLOCATED
0x00 1 10x1001xxxxxxxx UNALLOCATED
0x00 1 10x101xxxxxxxxx UNALLOCATED
0x00 1 10x11xxxxxxxxxx UNALLOCATED
0x00 1 10xx0000xxxxxxx Advanced SIMD load/store single structure
0x00 1 11xxxxxxxxxxxxx Advanced SIMD load/store single structure (post-indexed)
0x00 1 x0x00001xxxxxxx UNALLOCATED
0x00 1 x0x0001xxxxxxxx UNALLOCATED
0x00 1 x0x001xxxxxxxxx UNALLOCATED
0x00 1 x0x01xxxxxxxxxx UNALLOCATED
0x01 0 1xx1xxxxx000010 RCW compare and swap
0x01 0 1xx1xxxxx000011 RCW compare and swap pair
0x01 0 1xx1xxxxxxxxx00 128-bit atomic memory operations
1101 0 1000111110xxx11 GCS load/store
1101 0 1xx1xxxxxxxxxxx Load/store memory tags
1x00 0 00x1xxxxxxxxxxx Load/store exclusive pair
1x00 1 UNALLOCATED
xx00 0 00x0xxxxxxxxxxx Load/store exclusive register
xx00 0 01x0xxxxxxxxxxx Load/store ordered
xx00 0 01x1xxxxxxxxxxx Compare and swap
xx01 0 10x0xxxxxxxxx10 LDIAPP/STILP
xx01 0 11x000000000010 LDAPR/STLR (writeback)
xx01 0 1xx0xxxxxxxxx00 LDAPR/STLR (unscaled immediate)
xx01 1 1xx0xxxxxxxxx10 LDAPR/STLR (SIMD&FP)
xx01 0xxxxxxxxxxxxxx Load register (literal)
xx01 1xx0xxxxxxxxx01 Memory Copy and Memory Set
xx10 00xxxxxxxxxxxxx Load/store no-allocate pair (offset)
xx10 01xxxxxxxxxxxxx Load/store register pair (post-indexed)
xx10 10xxxxxxxxxxxxx Load/store register pair (offset)
xx10 11xxxxxxxxxxxxx Load/store register pair (pre-indexed)
xx11 0xx0xxxxxxxxx00 Load/store register (unscaled immediate)
xx11 0xx0xxxxxxxxx01 Load/store register (immediate post-indexed)
xx11 0xx0xxxxxxxxx10 Load/store register (unprivileged)
xx11 0xx0xxxxxxxxx11 Load/store register (immediate pre-indexed)
xx11 0xx1xxxxxxxxx00 Atomic memory operations
xx11 0xx1xxxxxxxxx10 Load/store register (register offset)
xx11 0xx1xxxxxxxxxx1 Load/store register (pac)
xx11 1xxxxxxxxxxxxxx Load/store register (unsigned immediate)

Compare and swap pair

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
0sz0010000L1Rso0Rt2RnRt
Decode fields Instruction Details Feature
sz L o0 Rt2
0xxxx UNALLOCATED-
10xxx UNALLOCATED-
110xx UNALLOCATED-
1110x UNALLOCATED-
11110 UNALLOCATED-
0 0 0 11111 CASP, CASPA, CASPAL, CASPL32-bit CASPFEAT_LSE
0 0 1 11111 CASP, CASPA, CASPAL, CASPL32-bit CASPLFEAT_LSE
0 1 0 11111 CASP, CASPA, CASPAL, CASPL32-bit CASPAFEAT_LSE
0 1 1 11111 CASP, CASPA, CASPAL, CASPL32-bit CASPALFEAT_LSE
1 0 0 11111 CASP, CASPA, CASPAL, CASPL64-bit CASPFEAT_LSE
1 0 1 11111 CASP, CASPA, CASPAL, CASPL64-bit CASPLFEAT_LSE
1 1 0 11111 CASP, CASPA, CASPAL, CASPL64-bit CASPAFEAT_LSE
1 1 1 11111 CASP, CASPA, CASPAL, CASPL64-bit CASPALFEAT_LSE

Advanced SIMD load/store multiple structures

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
0Q0011000L000000opcodesizeRnRt
Decode fields Instruction Details
L opcode
x0x1 UNALLOCATED
0101 UNALLOCATED
11xx UNALLOCATED
0 0000 ST4 (multiple structures)
0 0010 ST1 (multiple structures)Four registers
0 0100 ST3 (multiple structures)
0 0110 ST1 (multiple structures)Three registers
0 0111 ST1 (multiple structures)One register
0 1000 ST2 (multiple structures)
0 1010 ST1 (multiple structures)Two registers
1 0000 LD4 (multiple structures)
1 0010 LD1 (multiple structures)Four registers
1 0100 LD3 (multiple structures)
1 0110 LD1 (multiple structures)Three registers
1 0111 LD1 (multiple structures)One register
1 1000 LD2 (multiple structures)
1 1010 LD1 (multiple structures)Two registers

Advanced SIMD load/store multiple structures (post-indexed)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
0Q0011001L0RmopcodesizeRnRt
Decode fields Instruction Details
L Rm opcode
x0x1 UNALLOCATED
0101 UNALLOCATED
11xx UNALLOCATED
0 != 11111 0000 ST4 (multiple structures)Register offset
0 != 11111 0010 ST1 (multiple structures)Four registers, register offset
0 != 11111 0100 ST3 (multiple structures)Register offset
0 != 11111 0110 ST1 (multiple structures)Three registers, register offset
0 != 11111 0111 ST1 (multiple structures)One register, register offset
0 != 11111 1000 ST2 (multiple structures)Register offset
0 != 11111 1010 ST1 (multiple structures)Two registers, register offset
0 11111 0000 ST4 (multiple structures)Immediate offset
0 11111 0010 ST1 (multiple structures)Four registers, immediate offset
0 11111 0100 ST3 (multiple structures)Immediate offset
0 11111 0110 ST1 (multiple structures)Three registers, immediate offset
0 11111 0111 ST1 (multiple structures)One register, immediate offset
0 11111 1000 ST2 (multiple structures)Immediate offset
0 11111 1010 ST1 (multiple structures)Two registers, immediate offset
1 != 11111 0000 LD4 (multiple structures)Register offset
1 != 11111 0010 LD1 (multiple structures)Four registers, register offset
1 != 11111 0100 LD3 (multiple structures)Register offset
1 != 11111 0110 LD1 (multiple structures)Three registers, register offset
1 != 11111 0111 LD1 (multiple structures)One register, register offset
1 != 11111 1000 LD2 (multiple structures)Register offset
1 != 11111 1010 LD1 (multiple structures)Two registers, register offset
1 11111 0000 LD4 (multiple structures)Immediate offset
1 11111 0010 LD1 (multiple structures)Four registers, immediate offset
1 11111 0100 LD3 (multiple structures)Immediate offset
1 11111 0110 LD1 (multiple structures)Three registers, immediate offset
1 11111 0111 LD1 (multiple structures)One register, immediate offset
1 11111 1000 LD2 (multiple structures)Immediate offset
1 11111 1010 LD1 (multiple structures)Two registers, immediate offset

Advanced SIMD load/store single structure

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
0Q0011010LR0000o2opcodeSsizeRnRt
Decode fields Instruction Details Feature
L R o2 opcode S size
0 01x x1 UNALLOCATED-
0 10x 1x UNALLOCATED-
0 10x 1 01 UNALLOCATED-
0 1 0xx UNALLOCATED-
0 1 100 x0 UNALLOCATED-
0 1 100 11 UNALLOCATED-
0 1 100 1 01 UNALLOCATED-
0 1 101 UNALLOCATED-
0 1 11x UNALLOCATED-
1 1 UNALLOCATED-
0 0 11x UNALLOCATED-
0 0 0 000 ST1 (single structure)8-bit-
0 0 0 001 ST3 (single structure)8-bit-
0 0 0 010 x0 ST1 (single structure)16-bit-
0 0 0 011 x0 ST3 (single structure)16-bit-
0 0 0 100 00 ST1 (single structure)32-bit-
0 0 0 100 0 01 ST1 (single structure)64-bit-
0 0 0 101 00 ST3 (single structure)32-bit-
0 0 0 101 0 01 ST3 (single structure)64-bit-
0 0 1 100 0 01 STL1 (SIMD&FP)FEAT_LRCPC3
0 1 0 000 ST2 (single structure)8-bit-
0 1 0 001 ST4 (single structure)8-bit-
0 1 0 010 x0 ST2 (single structure)16-bit-
0 1 0 011 x0 ST4 (single structure)16-bit-
0 1 0 100 00 ST2 (single structure)32-bit-
0 1 0 100 0 01 ST2 (single structure)64-bit-
0 1 0 101 00 ST4 (single structure)32-bit-
0 1 0 101 0 01 ST4 (single structure)64-bit-
1 0 11x 1 UNALLOCATED-
1 0 0 000 LD1 (single structure)8-bit-
1 0 0 001 LD3 (single structure)8-bit-
1 0 0 010 x0 LD1 (single structure)16-bit-
1 0 0 011 x0 LD3 (single structure)16-bit-
1 0 0 100 00 LD1 (single structure)32-bit-
1 0 0 100 0 01 LD1 (single structure)64-bit-
1 0 0 101 00 LD3 (single structure)32-bit-
1 0 0 101 0 01 LD3 (single structure)64-bit-
1 0 0 110 0 LD1R-
1 0 0 111 0 LD3R-
1 0 1 100 0 01 LDAP1 (SIMD&FP)FEAT_LRCPC3
1 1 0 000 LD2 (single structure)8-bit-
1 1 0 001 LD4 (single structure)8-bit-
1 1 0 010 x0 LD2 (single structure)16-bit-
1 1 0 011 x0 LD4 (single structure)16-bit-
1 1 0 100 00 LD2 (single structure)32-bit-
1 1 0 100 0 01 LD2 (single structure)64-bit-
1 1 0 101 00 LD4 (single structure)32-bit-
1 1 0 101 0 01 LD4 (single structure)64-bit-
1 1 0 110 0 LD2R-
1 1 0 111 0 LD4R-

Advanced SIMD load/store single structure (post-indexed)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
0Q0011011LRRmopcodeSsizeRnRt
Decode fields Instruction Details
L R Rm opcode S size
01x x1 UNALLOCATED
10x 1x UNALLOCATED
10x 1 01 UNALLOCATED
0 11x UNALLOCATED
0 0 != 11111 000 ST1 (single structure)8-bit, register offset
0 0 != 11111 001 ST3 (single structure)8-bit, register offset
0 0 != 11111 010 x0 ST1 (single structure)16-bit, register offset
0 0 != 11111 011 x0 ST3 (single structure)16-bit, register offset
0 0 != 11111 100 00 ST1 (single structure)32-bit, register offset
0 0 != 11111 100 0 01 ST1 (single structure)64-bit, register offset
0 0 != 11111 101 00 ST3 (single structure)32-bit, register offset
0 0 != 11111 101 0 01 ST3 (single structure)64-bit, register offset
0 0 11111 000 ST1 (single structure)8-bit, immediate offset
0 0 11111 001 ST3 (single structure)8-bit, immediate offset
0 0 11111 010 x0 ST1 (single structure)16-bit, immediate offset
0 0 11111 011 x0 ST3 (single structure)16-bit, immediate offset
0 0 11111 100 00 ST1 (single structure)32-bit, immediate offset
0 0 11111 100 0 01 ST1 (single structure)64-bit, immediate offset
0 0 11111 101 00 ST3 (single structure)32-bit, immediate offset
0 0 11111 101 0 01 ST3 (single structure)64-bit, immediate offset
0 1 != 11111 000 ST2 (single structure)8-bit, register offset
0 1 != 11111 001 ST4 (single structure)8-bit, register offset
0 1 != 11111 010 x0 ST2 (single structure)16-bit, register offset
0 1 != 11111 011 x0 ST4 (single structure)16-bit, register offset
0 1 != 11111 100 00 ST2 (single structure)32-bit, register offset
0 1 != 11111 100 0 01 ST2 (single structure)64-bit, register offset
0 1 != 11111 101 00 ST4 (single structure)32-bit, register offset
0 1 != 11111 101 0 01 ST4 (single structure)64-bit, register offset
0 1 11111 000 ST2 (single structure)8-bit, immediate offset
0 1 11111 001 ST4 (single structure)8-bit, immediate offset
0 1 11111 010 x0 ST2 (single structure)16-bit, immediate offset
0 1 11111 011 x0 ST4 (single structure)16-bit, immediate offset
0 1 11111 100 00 ST2 (single structure)32-bit, immediate offset
0 1 11111 100 0 01 ST2 (single structure)64-bit, immediate offset
0 1 11111 101 00 ST4 (single structure)32-bit, immediate offset
0 1 11111 101 0 01 ST4 (single structure)64-bit, immediate offset
1 11x 1 UNALLOCATED
1 0 != 11111 000 LD1 (single structure)8-bit, register offset
1 0 != 11111 001 LD3 (single structure)8-bit, register offset
1 0 != 11111 010 x0 LD1 (single structure)16-bit, register offset
1 0 != 11111 011 x0 LD3 (single structure)16-bit, register offset
1 0 != 11111 100 00 LD1 (single structure)32-bit, register offset
1 0 != 11111 100 0 01 LD1 (single structure)64-bit, register offset
1 0 != 11111 101 00 LD3 (single structure)32-bit, register offset
1 0 != 11111 101 0 01 LD3 (single structure)64-bit, register offset
1 0 != 11111 110 0 LD1RRegister offset
1 0 != 11111 111 0 LD3RRegister offset
1 0 11111 000 LD1 (single structure)8-bit, immediate offset
1 0 11111 001 LD3 (single structure)8-bit, immediate offset
1 0 11111 010 x0 LD1 (single structure)16-bit, immediate offset
1 0 11111 011 x0 LD3 (single structure)16-bit, immediate offset
1 0 11111 100 00 LD1 (single structure)32-bit, immediate offset
1 0 11111 100 0 01 LD1 (single structure)64-bit, immediate offset
1 0 11111 101 00 LD3 (single structure)32-bit, immediate offset
1 0 11111 101 0 01 LD3 (single structure)64-bit, immediate offset
1 0 11111 110 0 LD1RImmediate offset
1 0 11111 111 0 LD3RImmediate offset
1 1 != 11111 000 LD2 (single structure)8-bit, register offset
1 1 != 11111 001 LD4 (single structure)8-bit, register offset
1 1 != 11111 010 x0 LD2 (single structure)16-bit, register offset
1 1 != 11111 011 x0 LD4 (single structure)16-bit, register offset
1 1 != 11111 100 00 LD2 (single structure)32-bit, register offset
1 1 != 11111 100 0 01 LD2 (single structure)64-bit, register offset
1 1 != 11111 101 00 LD4 (single structure)32-bit, register offset
1 1 != 11111 101 0 01 LD4 (single structure)64-bit, register offset
1 1 != 11111 110 0 LD2RRegister offset
1 1 != 11111 111 0 LD4RRegister offset
1 1 11111 000 LD2 (single structure)8-bit, immediate offset
1 1 11111 001 LD4 (single structure)8-bit, immediate offset
1 1 11111 010 x0 LD2 (single structure)16-bit, immediate offset
1 1 11111 011 x0 LD4 (single structure)16-bit, immediate offset
1 1 11111 100 00 LD2 (single structure)32-bit, immediate offset
1 1 11111 100 0 01 LD2 (single structure)64-bit, immediate offset
1 1 11111 101 00 LD4 (single structure)32-bit, immediate offset
1 1 11111 101 0 01 LD4 (single structure)64-bit, immediate offset
1 1 11111 110 0 LD2RImmediate offset
1 1 11111 111 0 LD4RImmediate offset

RCW compare and swap

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
0S011001AR1Rs000010RnRt
Decode fields Instruction Details Feature
S A R
0 0 0 RCWCAS, RCWCASA, RCWCASL, RCWCASALRCWCASFEAT_THE
0 0 1 RCWCAS, RCWCASA, RCWCASL, RCWCASALRCWCASLFEAT_THE
0 1 0 RCWCAS, RCWCASA, RCWCASL, RCWCASALRCWCASAFEAT_THE
0 1 1 RCWCAS, RCWCASA, RCWCASL, RCWCASALRCWCASALFEAT_THE
1 0 0 RCWSCAS, RCWSCASA, RCWSCASL, RCWSCASALRCWSCASFEAT_THE
1 0 1 RCWSCAS, RCWSCASA, RCWSCASL, RCWSCASALRCWSCASLFEAT_THE
1 1 0 RCWSCAS, RCWSCASA, RCWSCASL, RCWSCASALRCWSCASAFEAT_THE
1 1 1 RCWSCAS, RCWSCASA, RCWSCASL, RCWSCASALRCWSCASALFEAT_THE

RCW compare and swap pair

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
0S011001AR1Rs000011RnRt
Decode fields Instruction Details Feature
S A R
0 0 0 RCWCASP, RCWCASPA, RCWCASPL, RCWCASPALRCWCASPFEAT_D128 && FEAT_THE
0 0 1 RCWCASP, RCWCASPA, RCWCASPL, RCWCASPALRCWCASPLFEAT_D128 && FEAT_THE
0 1 0 RCWCASP, RCWCASPA, RCWCASPL, RCWCASPALRCWCASPAFEAT_D128 && FEAT_THE
0 1 1 RCWCASP, RCWCASPA, RCWCASPL, RCWCASPALRCWCASPALFEAT_D128 && FEAT_THE
1 0 0 RCWSCASP, RCWSCASPA, RCWSCASPL, RCWSCASPALRCWSCASPFEAT_D128 && FEAT_THE
1 0 1 RCWSCASP, RCWSCASPA, RCWSCASPL, RCWSCASPALRCWSCASPLFEAT_D128 && FEAT_THE
1 1 0 RCWSCASP, RCWSCASPA, RCWSCASPL, RCWSCASPALRCWSCASPAFEAT_D128 && FEAT_THE
1 1 1 RCWSCASP, RCWSCASPA, RCWSCASPL, RCWSCASPALRCWSCASPALFEAT_D128 && FEAT_THE

128-bit atomic memory operations

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
0S011001AR1Rt2o3opc00RnRt
Decode fields Instruction Details Feature
S A R o3 opc
1xx UNALLOCATED-
0 0 0x0 UNALLOCATED-
0 0 0 0 001 LDCLRP, LDCLRPA, LDCLRPAL, LDCLRPLLDCLRPFEAT_LSE128
0 0 0 0 011 LDSETP, LDSETPA, LDSETPAL, LDSETPLLDSETPFEAT_LSE128
0 0 0 1 000 SWPP, SWPPA, SWPPAL, SWPPLSWPPFEAT_LSE128
0 0 0 1 001 RCWCLRP, RCWCLRPA, RCWCLRPL, RCWCLRPALRCWCLRPFEAT_D128 && FEAT_THE
0 0 0 1 010 RCWSWPP, RCWSWPPA, RCWSWPPL, RCWSWPPALRCWSWPPFEAT_D128 && FEAT_THE
0 0 0 1 011 RCWSETP, RCWSETPA, RCWSETPL, RCWSETPALRCWSETPFEAT_D128 && FEAT_THE
0 0 1 0 001 LDCLRP, LDCLRPA, LDCLRPAL, LDCLRPLLDCLRPLFEAT_LSE128
0 0 1 0 011 LDSETP, LDSETPA, LDSETPAL, LDSETPLLDSETPLFEAT_LSE128
0 0 1 1 000 SWPP, SWPPA, SWPPAL, SWPPLSWPPLFEAT_LSE128
0 0 1 1 001 RCWCLRP, RCWCLRPA, RCWCLRPL, RCWCLRPALRCWCLRPLFEAT_D128 && FEAT_THE
0 0 1 1 010 RCWSWPP, RCWSWPPA, RCWSWPPL, RCWSWPPALRCWSWPPLFEAT_D128 && FEAT_THE
0 0 1 1 011 RCWSETP, RCWSETPA, RCWSETPL, RCWSETPALRCWSETPLFEAT_D128 && FEAT_THE
0 1 0 0 001 LDCLRP, LDCLRPA, LDCLRPAL, LDCLRPLLDCLRPAFEAT_LSE128
0 1 0 0 011 LDSETP, LDSETPA, LDSETPAL, LDSETPLLDSETPAFEAT_LSE128
0 1 0 1 000 SWPP, SWPPA, SWPPAL, SWPPLSWPPAFEAT_LSE128
0 1 0 1 001 RCWCLRP, RCWCLRPA, RCWCLRPL, RCWCLRPALRCWCLRPAFEAT_D128 && FEAT_THE
0 1 0 1 010 RCWSWPP, RCWSWPPA, RCWSWPPL, RCWSWPPALRCWSWPPAFEAT_D128 && FEAT_THE
0 1 0 1 011 RCWSETP, RCWSETPA, RCWSETPL, RCWSETPALRCWSETPAFEAT_D128 && FEAT_THE
0 1 1 0 001 LDCLRP, LDCLRPA, LDCLRPAL, LDCLRPLLDCLRPALFEAT_LSE128
0 1 1 0 011 LDSETP, LDSETPA, LDSETPAL, LDSETPLLDSETPALFEAT_LSE128
0 1 1 1 000 SWPP, SWPPA, SWPPAL, SWPPLSWPPALFEAT_LSE128
0 1 1 1 001 RCWCLRP, RCWCLRPA, RCWCLRPL, RCWCLRPALRCWCLRPALFEAT_D128 && FEAT_THE
0 1 1 1 010 RCWSWPP, RCWSWPPA, RCWSWPPL, RCWSWPPALRCWSWPPALFEAT_D128 && FEAT_THE
0 1 1 1 011 RCWSETP, RCWSETPA, RCWSETPL, RCWSETPALRCWSETPALFEAT_D128 && FEAT_THE
1 0 0xx UNALLOCATED-
1 1 000 UNALLOCATED-
1 0 0 1 001 RCWSCLRP, RCWSCLRPA, RCWSCLRPL, RCWSCLRPALRCWSCLRPFEAT_D128 && FEAT_THE
1 0 0 1 010 RCWSSWPP, RCWSSWPPA, RCWSSWPPL, RCWSSWPPALRCWSSWPPFEAT_D128 && FEAT_THE
1 0 0 1 011 RCWSSETP, RCWSSETPA, RCWSSETPL, RCWSSETPALRCWSSETPFEAT_D128 && FEAT_THE
1 0 1 1 001 RCWSCLRP, RCWSCLRPA, RCWSCLRPL, RCWSCLRPALRCWSCLRPLFEAT_D128 && FEAT_THE
1 0 1 1 010 RCWSSWPP, RCWSSWPPA, RCWSSWPPL, RCWSSWPPALRCWSSWPPLFEAT_D128 && FEAT_THE
1 0 1 1 011 RCWSSETP, RCWSSETPA, RCWSSETPL, RCWSSETPALRCWSSETPLFEAT_D128 && FEAT_THE
1 1 0 1 001 RCWSCLRP, RCWSCLRPA, RCWSCLRPL, RCWSCLRPALRCWSCLRPAFEAT_D128 && FEAT_THE
1 1 0 1 010 RCWSSWPP, RCWSSWPPA, RCWSSWPPL, RCWSSWPPALRCWSSWPPAFEAT_D128 && FEAT_THE
1 1 0 1 011 RCWSSETP, RCWSSETPA, RCWSSETPL, RCWSSETPALRCWSSETPAFEAT_D128 && FEAT_THE
1 1 1 1 001 RCWSCLRP, RCWSCLRPA, RCWSCLRPL, RCWSCLRPALRCWSCLRPALFEAT_D128 && FEAT_THE
1 1 1 1 010 RCWSSWPP, RCWSSWPPA, RCWSSWPPL, RCWSSWPPALRCWSSWPPALFEAT_D128 && FEAT_THE
1 1 1 1 011 RCWSSETP, RCWSSETPA, RCWSSETPL, RCWSSETPALRCWSSETPALFEAT_D128 && FEAT_THE

GCS load/store

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
11011001000111110opc11RnRt
Decode fields Instruction Details Feature
opc
000 GCSSTRFEAT_GCS
001 GCSSTTRFEAT_GCS
01x UNALLOCATED-
1xx UNALLOCATED-

Load/store memory tags

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
11011001opc1imm9op2RnRt
Decode fields Instruction Details Feature
opc imm9 op2
00 01 STGPost-indexFEAT_MTE
00 10 STGSigned offsetFEAT_MTE
00 11 STGPre-indexFEAT_MTE
00 000000000 00 STZGMFEAT_MTE2
00 000000001 00 UNALLOCATED-
00 00000001x 00 UNALLOCATED-
00 0000001xx 00 UNALLOCATED-
00 000001xxx 00 UNALLOCATED-
00 00001xxxx 00 UNALLOCATED-
00 0001xxxxx 00 UNALLOCATED-
00 001xxxxxx 00 UNALLOCATED-
00 01xxxxxxx 00 UNALLOCATED-
00 1xxxxxxxx 00 UNALLOCATED-
01 00 LDGFEAT_MTE
01 01 STZGPost-indexFEAT_MTE
01 10 STZGSigned offsetFEAT_MTE
01 11 STZGPre-indexFEAT_MTE
1x 000000001 00 UNALLOCATED-
1x 00000001x 00 UNALLOCATED-
1x 0000001xx 00 UNALLOCATED-
1x 000001xxx 00 UNALLOCATED-
1x 00001xxxx 00 UNALLOCATED-
1x 0001xxxxx 00 UNALLOCATED-
1x 001xxxxxx 00 UNALLOCATED-
1x 01xxxxxxx 00 UNALLOCATED-
1x 1xxxxxxxx 00 UNALLOCATED-
10 01 ST2GPost-indexFEAT_MTE
10 10 ST2GSigned offsetFEAT_MTE
10 11 ST2GPre-indexFEAT_MTE
10 000000000 00 STGMFEAT_MTE2
11 01 STZ2GPost-indexFEAT_MTE
11 10 STZ2GSigned offsetFEAT_MTE
11 11 STZ2GPre-indexFEAT_MTE
11 000000000 00 LDGMFEAT_MTE2

Load/store exclusive pair

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
1sz0010000L1Rso0Rt2RnRt
Decode fields Instruction Details
sz L o0
0 0 0 STXP32-bit
0 0 1 STLXP32-bit
0 1 0 LDXP32-bit
0 1 1 LDAXP32-bit
1 0 0 STXP64-bit
1 0 1 STLXP64-bit
1 1 0 LDXP64-bit
1 1 1 LDAXP64-bit

Load/store exclusive register

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
size0010000L0Rso0Rt2RnRt
Decode fields Instruction Details
size L o0
00 0 0 STXRB
00 0 1 STLXRB
00 1 0 LDXRB
00 1 1 LDAXRB
01 0 0 STXRH
01 0 1 STLXRH
01 1 0 LDXRH
01 1 1 LDAXRH
10 0 0 STXR32-bit
10 0 1 STLXR32-bit
10 1 0 LDXR32-bit
10 1 1 LDAXR32-bit
11 0 0 STXR64-bit
11 0 1 STLXR64-bit
11 1 0 LDXR64-bit
11 1 1 LDAXR64-bit

Load/store ordered

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
size0010001L0Rso0Rt2RnRt
Decode fields Instruction Details Feature
size L o0
00 0 0 STLLRBFEAT_LOR
00 0 1 STLRB-
00 1 0 LDLARBFEAT_LOR
00 1 1 LDARB-
01 0 0 STLLRHFEAT_LOR
01 0 1 STLRH-
01 1 0 LDLARHFEAT_LOR
01 1 1 LDARH-
10 0 0 STLLR32-bitFEAT_LOR
10 0 1 STLR32-bit-
10 1 0 LDLAR32-bitFEAT_LOR
10 1 1 LDAR32-bit-
11 0 0 STLLR64-bitFEAT_LOR
11 0 1 STLR64-bit-
11 1 0 LDLAR64-bitFEAT_LOR
11 1 1 LDAR64-bit-

Compare and swap

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
size0010001L1Rso0Rt2RnRt
Decode fields Instruction Details Feature
size L o0 Rt2
0xxxx UNALLOCATED-
10xxx UNALLOCATED-
110xx UNALLOCATED-
1110x UNALLOCATED-
11110 UNALLOCATED-
00 0 0 11111 CASB, CASAB, CASALB, CASLBCASBFEAT_LSE
00 0 1 11111 CASB, CASAB, CASALB, CASLBCASLBFEAT_LSE
00 1 0 11111 CASB, CASAB, CASALB, CASLBCASABFEAT_LSE
00 1 1 11111 CASB, CASAB, CASALB, CASLBCASALBFEAT_LSE
01 0 0 11111 CASH, CASAH, CASALH, CASLHCASHFEAT_LSE
01 0 1 11111 CASH, CASAH, CASALH, CASLHCASLHFEAT_LSE
01 1 0 11111 CASH, CASAH, CASALH, CASLHCASAHFEAT_LSE
01 1 1 11111 CASH, CASAH, CASALH, CASLHCASALHFEAT_LSE
10 0 0 11111 CAS, CASA, CASAL, CASL32-bit CASFEAT_LSE
10 0 1 11111 CAS, CASA, CASAL, CASL32-bit CASLFEAT_LSE
10 1 0 11111 CAS, CASA, CASAL, CASL32-bit CASAFEAT_LSE
10 1 1 11111 CAS, CASA, CASAL, CASL32-bit CASALFEAT_LSE
11 0 0 11111 CAS, CASA, CASAL, CASL64-bit CASFEAT_LSE
11 0 1 11111 CAS, CASA, CASAL, CASL64-bit CASLFEAT_LSE
11 1 0 11111 CAS, CASA, CASAL, CASL64-bit CASAFEAT_LSE
11 1 1 11111 CAS, CASA, CASAL, CASL64-bit CASALFEAT_LSE

LDIAPP/STILP

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
size0110010L0Rt2opc210RnRt
Decode fields Instruction Details Feature
size L opc2
0x UNALLOCATED-
1x 001x UNALLOCATED-
1x 01xx UNALLOCATED-
1x 1xxx UNALLOCATED-
10 0 0000 STILP32-bit pre-indexFEAT_LRCPC3
10 0 0001 STILP32-bitFEAT_LRCPC3
10 1 0000 LDIAPP32-bit post-indexFEAT_LRCPC3
10 1 0001 LDIAPP32-bitFEAT_LRCPC3
11 0 0000 STILP64-bit pre-indexFEAT_LRCPC3
11 0 0001 STILP64-bitFEAT_LRCPC3
11 1 0000 LDIAPP64-bit post-indexFEAT_LRCPC3
11 1 0001 LDIAPP64-bitFEAT_LRCPC3

LDAPR/STLR (writeback)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
size0110011L000000000010RnRt
Decode fields Instruction Details Feature
size L
0x UNALLOCATED-
10 0 STLR32-bitFEAT_LRCPC3
10 1 LDAPR32-bitFEAT_LRCPC3
11 0 STLR64-bitFEAT_LRCPC3
11 1 LDAPR64-bitFEAT_LRCPC3

LDAPR/STLR (unscaled immediate)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
size011001opc0imm900RnRt
Decode fields Instruction Details Feature
size opc
00 00 STLURBFEAT_LRCPC2
00 01 LDAPURBFEAT_LRCPC2
00 10 LDAPURSB64-bitFEAT_LRCPC2
00 11 LDAPURSB32-bitFEAT_LRCPC2
01 00 STLURHFEAT_LRCPC2
01 01 LDAPURHFEAT_LRCPC2
01 10 LDAPURSH64-bitFEAT_LRCPC2
01 11 LDAPURSH32-bitFEAT_LRCPC2
10 00 STLUR32-bitFEAT_LRCPC2
10 01 LDAPUR32-bitFEAT_LRCPC2
10 10 LDAPURSWFEAT_LRCPC2
10 11 UNALLOCATED-
11 00 STLUR64-bitFEAT_LRCPC2
11 01 LDAPUR64-bitFEAT_LRCPC2
11 1x UNALLOCATED-

LDAPR/STLR (SIMD&FP)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
size011101opc0imm910RnRt
Decode fields Instruction Details Feature
size opc
00 00 STLUR (SIMD&FP)8-bitFEAT_LRCPC3
00 01 LDAPUR (SIMD&FP)8-bitFEAT_LRCPC3
00 10 STLUR (SIMD&FP)128-bitFEAT_LRCPC3
00 11 LDAPUR (SIMD&FP)128-bitFEAT_LRCPC3
01 00 STLUR (SIMD&FP)16-bitFEAT_LRCPC3
01 01 LDAPUR (SIMD&FP)16-bitFEAT_LRCPC3
01 1x UNALLOCATED-
1x 1x UNALLOCATED-
10 00 STLUR (SIMD&FP)32-bitFEAT_LRCPC3
10 01 LDAPUR (SIMD&FP)32-bitFEAT_LRCPC3
11 00 STLUR (SIMD&FP)64-bitFEAT_LRCPC3
11 01 LDAPUR (SIMD&FP)64-bitFEAT_LRCPC3

Load register (literal)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
opc011VR00imm19Rt
Decode fields Instruction Details
opc VR
00 0 LDR (literal)32-bit
00 1 LDR (literal, SIMD&FP)32-bit
01 0 LDR (literal)64-bit
01 1 LDR (literal, SIMD&FP)64-bit
10 0 LDRSW (literal)
10 1 LDR (literal, SIMD&FP)128-bit
11 0 PRFM (literal)
11 1 UNALLOCATED

Memory Copy and Memory Set

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
size011o001op10Rsop201RnRd
Decode fields Instruction Details Feature
o0 op1 op2
11 11xx UNALLOCATED-
0 00 0000 CPYFP, CPYFM, CPYFEPrologueFEAT_MOPS
0 00 0001 CPYFPWT, CPYFMWT, CPYFEWTPrologueFEAT_MOPS
0 00 0010 CPYFPRT, CPYFMRT, CPYFERTPrologueFEAT_MOPS
0 00 0011 CPYFPT, CPYFMT, CPYFETPrologueFEAT_MOPS
0 00 0100 CPYFPWN, CPYFMWN, CPYFEWNPrologueFEAT_MOPS
0 00 0101 CPYFPWTWN, CPYFMWTWN, CPYFEWTWNPrologueFEAT_MOPS
0 00 0110 CPYFPRTWN, CPYFMRTWN, CPYFERTWNPrologueFEAT_MOPS
0 00 0111 CPYFPTWN, CPYFMTWN, CPYFETWNPrologueFEAT_MOPS
0 00 1000 CPYFPRN, CPYFMRN, CPYFERNPrologueFEAT_MOPS
0 00 1001 CPYFPWTRN, CPYFMWTRN, CPYFEWTRNPrologueFEAT_MOPS
0 00 1010 CPYFPRTRN, CPYFMRTRN, CPYFERTRNPrologueFEAT_MOPS
0 00 1011 CPYFPTRN, CPYFMTRN, CPYFETRNPrologueFEAT_MOPS
0 00 1100 CPYFPN, CPYFMN, CPYFENPrologueFEAT_MOPS
0 00 1101 CPYFPWTN, CPYFMWTN, CPYFEWTNPrologueFEAT_MOPS
0 00 1110 CPYFPRTN, CPYFMRTN, CPYFERTNPrologueFEAT_MOPS
0 00 1111 CPYFPTN, CPYFMTN, CPYFETNPrologueFEAT_MOPS
0 01 0000 CPYFP, CPYFM, CPYFEMainFEAT_MOPS
0 01 0001 CPYFPWT, CPYFMWT, CPYFEWTMainFEAT_MOPS
0 01 0010 CPYFPRT, CPYFMRT, CPYFERTMainFEAT_MOPS
0 01 0011 CPYFPT, CPYFMT, CPYFETMainFEAT_MOPS
0 01 0100 CPYFPWN, CPYFMWN, CPYFEWNMainFEAT_MOPS
0 01 0101 CPYFPWTWN, CPYFMWTWN, CPYFEWTWNMainFEAT_MOPS
0 01 0110 CPYFPRTWN, CPYFMRTWN, CPYFERTWNMainFEAT_MOPS
0 01 0111 CPYFPTWN, CPYFMTWN, CPYFETWNMainFEAT_MOPS
0 01 1000 CPYFPRN, CPYFMRN, CPYFERNMainFEAT_MOPS
0 01 1001 CPYFPWTRN, CPYFMWTRN, CPYFEWTRNMainFEAT_MOPS
0 01 1010 CPYFPRTRN, CPYFMRTRN, CPYFERTRNMainFEAT_MOPS
0 01 1011 CPYFPTRN, CPYFMTRN, CPYFETRNMainFEAT_MOPS
0 01 1100 CPYFPN, CPYFMN, CPYFENMainFEAT_MOPS
0 01 1101 CPYFPWTN, CPYFMWTN, CPYFEWTNMainFEAT_MOPS
0 01 1110 CPYFPRTN, CPYFMRTN, CPYFERTNMainFEAT_MOPS
0 01 1111 CPYFPTN, CPYFMTN, CPYFETNMainFEAT_MOPS
0 10 0000 CPYFP, CPYFM, CPYFEEpilogueFEAT_MOPS
0 10 0001 CPYFPWT, CPYFMWT, CPYFEWTEpilogueFEAT_MOPS
0 10 0010 CPYFPRT, CPYFMRT, CPYFERTEpilogueFEAT_MOPS
0 10 0011 CPYFPT, CPYFMT, CPYFETEpilogueFEAT_MOPS
0 10 0100 CPYFPWN, CPYFMWN, CPYFEWNEpilogueFEAT_MOPS
0 10 0101 CPYFPWTWN, CPYFMWTWN, CPYFEWTWNEpilogueFEAT_MOPS
0 10 0110 CPYFPRTWN, CPYFMRTWN, CPYFERTWNEpilogueFEAT_MOPS
0 10 0111 CPYFPTWN, CPYFMTWN, CPYFETWNEpilogueFEAT_MOPS
0 10 1000 CPYFPRN, CPYFMRN, CPYFERNEpilogueFEAT_MOPS
0 10 1001 CPYFPWTRN, CPYFMWTRN, CPYFEWTRNEpilogueFEAT_MOPS
0 10 1010 CPYFPRTRN, CPYFMRTRN, CPYFERTRNEpilogueFEAT_MOPS
0 10 1011 CPYFPTRN, CPYFMTRN, CPYFETRNEpilogueFEAT_MOPS
0 10 1100 CPYFPN, CPYFMN, CPYFENEpilogueFEAT_MOPS
0 10 1101 CPYFPWTN, CPYFMWTN, CPYFEWTNEpilogueFEAT_MOPS
0 10 1110 CPYFPRTN, CPYFMRTN, CPYFERTNEpilogueFEAT_MOPS
0 10 1111 CPYFPTN, CPYFMTN, CPYFETNEpilogueFEAT_MOPS
0 11 0000 SETP, SETM, SETEPrologueFEAT_MOPS
0 11 0001 SETPT, SETMT, SETETPrologueFEAT_MOPS
0 11 0010 SETPN, SETMN, SETENPrologueFEAT_MOPS
0 11 0011 SETPTN, SETMTN, SETETNPrologueFEAT_MOPS
0 11 0100 SETP, SETM, SETEMainFEAT_MOPS
0 11 0101 SETPT, SETMT, SETETMainFEAT_MOPS
0 11 0110 SETPN, SETMN, SETENMainFEAT_MOPS
0 11 0111 SETPTN, SETMTN, SETETNMainFEAT_MOPS
0 11 1000 SETP, SETM, SETEEpilogueFEAT_MOPS
0 11 1001 SETPT, SETMT, SETETEpilogueFEAT_MOPS
0 11 1010 SETPN, SETMN, SETENEpilogueFEAT_MOPS
0 11 1011 SETPTN, SETMTN, SETETNEpilogueFEAT_MOPS
1 00 0000 CPYP, CPYM, CPYEPrologueFEAT_MOPS
1 00 0001 CPYPWT, CPYMWT, CPYEWTPrologueFEAT_MOPS
1 00 0010 CPYPRT, CPYMRT, CPYERTPrologueFEAT_MOPS
1 00 0011 CPYPT, CPYMT, CPYETPrologueFEAT_MOPS
1 00 0100 CPYPWN, CPYMWN, CPYEWNPrologueFEAT_MOPS
1 00 0101 CPYPWTWN, CPYMWTWN, CPYEWTWNPrologueFEAT_MOPS
1 00 0110 CPYPRTWN, CPYMRTWN, CPYERTWNPrologueFEAT_MOPS
1 00 0111 CPYPTWN, CPYMTWN, CPYETWNPrologueFEAT_MOPS
1 00 1000 CPYPRN, CPYMRN, CPYERNPrologueFEAT_MOPS
1 00 1001 CPYPWTRN, CPYMWTRN, CPYEWTRNPrologueFEAT_MOPS
1 00 1010 CPYPRTRN, CPYMRTRN, CPYERTRNPrologueFEAT_MOPS
1 00 1011 CPYPTRN, CPYMTRN, CPYETRNPrologueFEAT_MOPS
1 00 1100 CPYPN, CPYMN, CPYENPrologueFEAT_MOPS
1 00 1101 CPYPWTN, CPYMWTN, CPYEWTNPrologueFEAT_MOPS
1 00 1110 CPYPRTN, CPYMRTN, CPYERTNPrologueFEAT_MOPS
1 00 1111 CPYPTN, CPYMTN, CPYETNPrologueFEAT_MOPS
1 01 0000 CPYP, CPYM, CPYEMainFEAT_MOPS
1 01 0001 CPYPWT, CPYMWT, CPYEWTMainFEAT_MOPS
1 01 0010 CPYPRT, CPYMRT, CPYERTMainFEAT_MOPS
1 01 0011 CPYPT, CPYMT, CPYETMainFEAT_MOPS
1 01 0100 CPYPWN, CPYMWN, CPYEWNMainFEAT_MOPS
1 01 0101 CPYPWTWN, CPYMWTWN, CPYEWTWNMainFEAT_MOPS
1 01 0110 CPYPRTWN, CPYMRTWN, CPYERTWNMainFEAT_MOPS
1 01 0111 CPYPTWN, CPYMTWN, CPYETWNMainFEAT_MOPS
1 01 1000 CPYPRN, CPYMRN, CPYERNMainFEAT_MOPS
1 01 1001 CPYPWTRN, CPYMWTRN, CPYEWTRNMainFEAT_MOPS
1 01 1010 CPYPRTRN, CPYMRTRN, CPYERTRNMainFEAT_MOPS
1 01 1011 CPYPTRN, CPYMTRN, CPYETRNMainFEAT_MOPS
1 01 1100 CPYPN, CPYMN, CPYENMainFEAT_MOPS
1 01 1101 CPYPWTN, CPYMWTN, CPYEWTNMainFEAT_MOPS
1 01 1110 CPYPRTN, CPYMRTN, CPYERTNMainFEAT_MOPS
1 01 1111 CPYPTN, CPYMTN, CPYETNMainFEAT_MOPS
1 10 0000 CPYP, CPYM, CPYEEpilogueFEAT_MOPS
1 10 0001 CPYPWT, CPYMWT, CPYEWTEpilogueFEAT_MOPS
1 10 0010 CPYPRT, CPYMRT, CPYERTEpilogueFEAT_MOPS
1 10 0011 CPYPT, CPYMT, CPYETEpilogueFEAT_MOPS
1 10 0100 CPYPWN, CPYMWN, CPYEWNEpilogueFEAT_MOPS
1 10 0101 CPYPWTWN, CPYMWTWN, CPYEWTWNEpilogueFEAT_MOPS
1 10 0110 CPYPRTWN, CPYMRTWN, CPYERTWNEpilogueFEAT_MOPS
1 10 0111 CPYPTWN, CPYMTWN, CPYETWNEpilogueFEAT_MOPS
1 10 1000 CPYPRN, CPYMRN, CPYERNEpilogueFEAT_MOPS
1 10 1001 CPYPWTRN, CPYMWTRN, CPYEWTRNEpilogueFEAT_MOPS
1 10 1010 CPYPRTRN, CPYMRTRN, CPYERTRNEpilogueFEAT_MOPS
1 10 1011 CPYPTRN, CPYMTRN, CPYETRNEpilogueFEAT_MOPS
1 10 1100 CPYPN, CPYMN, CPYENEpilogueFEAT_MOPS
1 10 1101 CPYPWTN, CPYMWTN, CPYEWTNEpilogueFEAT_MOPS
1 10 1110 CPYPRTN, CPYMRTN, CPYERTNEpilogueFEAT_MOPS
1 10 1111 CPYPTN, CPYMTN, CPYETNEpilogueFEAT_MOPS
1 11 0000 SETGP, SETGM, SETGEPrologueFEAT_MOPS
1 11 0001 SETGPT, SETGMT, SETGETPrologueFEAT_MOPS
1 11 0010 SETGPN, SETGMN, SETGENPrologueFEAT_MOPS
1 11 0011 SETGPTN, SETGMTN, SETGETNPrologueFEAT_MOPS
1 11 0100 SETGP, SETGM, SETGEMainFEAT_MOPS
1 11 0101 SETGPT, SETGMT, SETGETMainFEAT_MOPS
1 11 0110 SETGPN, SETGMN, SETGENMainFEAT_MOPS
1 11 0111 SETGPTN, SETGMTN, SETGETNMainFEAT_MOPS
1 11 1000 SETGP, SETGM, SETGEEpilogueFEAT_MOPS
1 11 1001 SETGPT, SETGMT, SETGETEpilogueFEAT_MOPS
1 11 1010 SETGPN, SETGMN, SETGENEpilogueFEAT_MOPS
1 11 1011 SETGPTN, SETGMTN, SETGETNEpilogueFEAT_MOPS

Load/store no-allocate pair (offset)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
opc101VR000Limm7Rt2RnRt
Decode fields Instruction Details
opc VR L
00 0 0 STNP32-bit
00 0 1 LDNP32-bit
00 1 0 STNP (SIMD&FP)32-bit
00 1 1 LDNP (SIMD&FP)32-bit
01 0 UNALLOCATED
01 1 0 STNP (SIMD&FP)64-bit
01 1 1 LDNP (SIMD&FP)64-bit
10 0 0 STNP64-bit
10 0 1 LDNP64-bit
10 1 0 STNP (SIMD&FP)128-bit
10 1 1 LDNP (SIMD&FP)128-bit
11 UNALLOCATED

Load/store register pair (post-indexed)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
opc101VR001Limm7Rt2RnRt
Decode fields Instruction Details Feature
opc VR L
00 0 0 STP32-bit-
00 0 1 LDP32-bit-
00 1 0 STP (SIMD&FP)32-bit-
00 1 1 LDP (SIMD&FP)32-bit-
01 0 0 STGPFEAT_MTE
01 0 1 LDPSW-
01 1 0 STP (SIMD&FP)64-bit-
01 1 1 LDP (SIMD&FP)64-bit-
10 0 0 STP64-bit-
10 0 1 LDP64-bit-
10 1 0 STP (SIMD&FP)128-bit-
10 1 1 LDP (SIMD&FP)128-bit-
11 UNALLOCATED-

Load/store register pair (offset)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
opc101VR010Limm7Rt2RnRt
Decode fields Instruction Details Feature
opc VR L
00 0 0 STP32-bit-
00 0 1 LDP32-bit-
00 1 0 STP (SIMD&FP)32-bit-
00 1 1 LDP (SIMD&FP)32-bit-
01 0 0 STGPFEAT_MTE
01 0 1 LDPSW-
01 1 0 STP (SIMD&FP)64-bit-
01 1 1 LDP (SIMD&FP)64-bit-
10 0 0 STP64-bit-
10 0 1 LDP64-bit-
10 1 0 STP (SIMD&FP)128-bit-
10 1 1 LDP (SIMD&FP)128-bit-
11 UNALLOCATED-

Load/store register pair (pre-indexed)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
opc101VR011Limm7Rt2RnRt
Decode fields Instruction Details Feature
opc VR L
00 0 0 STP32-bit-
00 0 1 LDP32-bit-
00 1 0 STP (SIMD&FP)32-bit-
00 1 1 LDP (SIMD&FP)32-bit-
01 0 0 STGPFEAT_MTE
01 0 1 LDPSW-
01 1 0 STP (SIMD&FP)64-bit-
01 1 1 LDP (SIMD&FP)64-bit-
10 0 0 STP64-bit-
10 0 1 LDP64-bit-
10 1 0 STP (SIMD&FP)128-bit-
10 1 1 LDP (SIMD&FP)128-bit-
11 UNALLOCATED-

Load/store register (unscaled immediate)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
size111VR00opc0imm900RnRt
Decode fields Instruction Details
size VR opc
00 0 00 STURB
00 0 01 LDURB
00 0 10 LDURSB64-bit
00 0 11 LDURSB32-bit
00 1 00 STUR (SIMD&FP)8-bit
00 1 01 LDUR (SIMD&FP)8-bit
00 1 10 STUR (SIMD&FP)128-bit
00 1 11 LDUR (SIMD&FP)128-bit
01 0 00 STURH
01 0 01 LDURH
01 0 10 LDURSH64-bit
01 0 11 LDURSH32-bit
01 1 00 STUR (SIMD&FP)16-bit
01 1 01 LDUR (SIMD&FP)16-bit
01 1 1x UNALLOCATED
1x 0 11 UNALLOCATED
1x 1 1x UNALLOCATED
10 0 00 STUR32-bit
10 0 01 LDUR32-bit
10 0 10 LDURSW
10 1 00 STUR (SIMD&FP)32-bit
10 1 01 LDUR (SIMD&FP)32-bit
11 0 00 STUR64-bit
11 0 01 LDUR64-bit
11 0 10 PRFUM
11 1 00 STUR (SIMD&FP)64-bit
11 1 01 LDUR (SIMD&FP)64-bit

Load/store register (immediate post-indexed)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
size111VR00opc0imm901RnRt
Decode fields Instruction Details
size VR opc
00 0 00 STRB (immediate)
00 0 01 LDRB (immediate)
00 0 10 LDRSB (immediate)64-bit
00 0 11 LDRSB (immediate)32-bit
00 1 00 STR (immediate, SIMD&FP)8-bit
00 1 01 LDR (immediate, SIMD&FP)8-bit
00 1 10 STR (immediate, SIMD&FP)128-bit
00 1 11 LDR (immediate, SIMD&FP)128-bit
01 0 00 STRH (immediate)
01 0 01 LDRH (immediate)
01 0 10 LDRSH (immediate)64-bit
01 0 11 LDRSH (immediate)32-bit
01 1 00 STR (immediate, SIMD&FP)16-bit
01 1 01 LDR (immediate, SIMD&FP)16-bit
01 1 1x UNALLOCATED
10 0 00 STR (immediate)32-bit
10 0 01 LDR (immediate)32-bit
10 0 10 LDRSW (immediate)
10 0 11 UNALLOCATED
10 1 00 STR (immediate, SIMD&FP)32-bit
10 1 01 LDR (immediate, SIMD&FP)32-bit
10 1 1x UNALLOCATED
11 1x UNALLOCATED
11 0 00 STR (immediate)64-bit
11 0 01 LDR (immediate)64-bit
11 1 00 STR (immediate, SIMD&FP)64-bit
11 1 01 LDR (immediate, SIMD&FP)64-bit

Load/store register (unprivileged)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
size111VR00opc0imm910RnRt
Decode fields Instruction Details
size VR opc
1 UNALLOCATED
00 0 00 STTRB
00 0 01 LDTRB
00 0 10 LDTRSB64-bit
00 0 11 LDTRSB32-bit
01 0 00 STTRH
01 0 01 LDTRH
01 0 10 LDTRSH64-bit
01 0 11 LDTRSH32-bit
10 0 00 STTR32-bit
10 0 01 LDTR32-bit
10 0 10 LDTRSW
10 0 11 UNALLOCATED
11 0 00 STTR64-bit
11 0 01 LDTR64-bit
11 0 1x UNALLOCATED

Load/store register (immediate pre-indexed)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
size111VR00opc0imm911RnRt
Decode fields Instruction Details
size VR opc
00 0 00 STRB (immediate)
00 0 01 LDRB (immediate)
00 0 10 LDRSB (immediate)64-bit
00 0 11 LDRSB (immediate)32-bit
00 1 00 STR (immediate, SIMD&FP)8-bit
00 1 01 LDR (immediate, SIMD&FP)8-bit
00 1 10 STR (immediate, SIMD&FP)128-bit
00 1 11 LDR (immediate, SIMD&FP)128-bit
01 0 00 STRH (immediate)
01 0 01 LDRH (immediate)
01 0 10 LDRSH (immediate)64-bit
01 0 11 LDRSH (immediate)32-bit
01 1 00 STR (immediate, SIMD&FP)16-bit
01 1 01 LDR (immediate, SIMD&FP)16-bit
01 1 1x UNALLOCATED
10 0 00 STR (immediate)32-bit
10 0 01 LDR (immediate)32-bit
10 0 10 LDRSW (immediate)
10 0 11 UNALLOCATED
10 1 00 STR (immediate, SIMD&FP)32-bit
10 1 01 LDR (immediate, SIMD&FP)32-bit
10 1 1x UNALLOCATED
11 1x UNALLOCATED
11 0 00 STR (immediate)64-bit
11 0 01 LDR (immediate)64-bit
11 1 00 STR (immediate, SIMD&FP)64-bit
11 1 01 LDR (immediate, SIMD&FP)64-bit

Atomic memory operations

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
size111VR00AR1Rso3opc00RnRt
Decode fields Instruction Details Feature
size VR A R Rs o3 opc
0 0 1 11x UNALLOCATED-
0 1 1 1xx UNALLOCATED-
0 0 0 1 100 UNALLOCATED-
1 UNALLOCATED-
0x 0 0 1 101 UNALLOCATED-
00 0 0 0 0 000 LDADDB, LDADDAB, LDADDALB, LDADDLBNo memory orderingFEAT_LSE
00 0 0 0 0 001 LDCLRB, LDCLRAB, LDCLRALB, LDCLRLBNo memory orderingFEAT_LSE
00 0 0 0 0 010 LDEORB, LDEORAB, LDEORALB, LDEORLBNo memory orderingFEAT_LSE
00 0 0 0 0 011 LDSETB, LDSETAB, LDSETALB, LDSETLBNo memory orderingFEAT_LSE
00 0 0 0 0 100 LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLBNo memory orderingFEAT_LSE
00 0 0 0 0 101 LDSMINB, LDSMINAB, LDSMINALB, LDSMINLBNo memory orderingFEAT_LSE
00 0 0 0 0 110 LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLBNo memory orderingFEAT_LSE
00 0 0 0 0 111 LDUMINB, LDUMINAB, LDUMINALB, LDUMINLBNo memory orderingFEAT_LSE
00 0 0 0 1 000 SWPB, SWPAB, SWPALB, SWPLBSWPBFEAT_LSE
00 0 0 0 1 001 RCWCLR, RCWCLRA, RCWCLRL, RCWCLRALRCWCLRFEAT_THE
00 0 0 0 1 010 RCWSWP, RCWSWPA, RCWSWPL, RCWSWPALRCWSWPFEAT_THE
00 0 0 0 1 011 RCWSET, RCWSETA, RCWSETL, RCWSETALRCWSETFEAT_THE
00 0 0 1 0 000 LDADDB, LDADDAB, LDADDALB, LDADDLBReleaseFEAT_LSE
00 0 0 1 0 001 LDCLRB, LDCLRAB, LDCLRALB, LDCLRLBReleaseFEAT_LSE
00 0 0 1 0 010 LDEORB, LDEORAB, LDEORALB, LDEORLBReleaseFEAT_LSE
00 0 0 1 0 011 LDSETB, LDSETAB, LDSETALB, LDSETLBReleaseFEAT_LSE
00 0 0 1 0 100 LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLBReleaseFEAT_LSE
00 0 0 1 0 101 LDSMINB, LDSMINAB, LDSMINALB, LDSMINLBReleaseFEAT_LSE
00 0 0 1 0 110 LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLBReleaseFEAT_LSE
00 0 0 1 0 111 LDUMINB, LDUMINAB, LDUMINALB, LDUMINLBReleaseFEAT_LSE
00 0 0 1 1 000 SWPB, SWPAB, SWPALB, SWPLBSWPLBFEAT_LSE
00 0 0 1 1 001 RCWCLR, RCWCLRA, RCWCLRL, RCWCLRALRCWCLRLFEAT_THE
00 0 0 1 1 010 RCWSWP, RCWSWPA, RCWSWPL, RCWSWPALRCWSWPLFEAT_THE
00 0 0 1 1 011 RCWSET, RCWSETA, RCWSETL, RCWSETALRCWSETLFEAT_THE
00 0 1 0 0 000 LDADDB, LDADDAB, LDADDALB, LDADDLBAcquireFEAT_LSE
00 0 1 0 0 001 LDCLRB, LDCLRAB, LDCLRALB, LDCLRLBAcquireFEAT_LSE
00 0 1 0 0 010 LDEORB, LDEORAB, LDEORALB, LDEORLBAcquireFEAT_LSE
00 0 1 0 0 011 LDSETB, LDSETAB, LDSETALB, LDSETLBAcquireFEAT_LSE
00 0 1 0 0 100 LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLBAcquireFEAT_LSE
00 0 1 0 0 101 LDSMINB, LDSMINAB, LDSMINALB, LDSMINLBAcquireFEAT_LSE
00 0 1 0 0 110 LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLBAcquireFEAT_LSE
00 0 1 0 0 111 LDUMINB, LDUMINAB, LDUMINALB, LDUMINLBAcquireFEAT_LSE
00 0 1 0 1 000 SWPB, SWPAB, SWPALB, SWPLBSWPABFEAT_LSE
00 0 1 0 1 001 RCWCLR, RCWCLRA, RCWCLRL, RCWCLRALRCWCLRAFEAT_THE
00 0 1 0 1 010 RCWSWP, RCWSWPA, RCWSWPL, RCWSWPALRCWSWPAFEAT_THE
00 0 1 0 1 011 RCWSET, RCWSETA, RCWSETL, RCWSETALRCWSETAFEAT_THE
00 0 1 0 1 100 LDAPRBFEAT_LRCPC
00 0 1 1 0 000 LDADDB, LDADDAB, LDADDALB, LDADDLBAcquire-releaseFEAT_LSE
00 0 1 1 0 001 LDCLRB, LDCLRAB, LDCLRALB, LDCLRLBAcquire-releaseFEAT_LSE
00 0 1 1 0 010 LDEORB, LDEORAB, LDEORALB, LDEORLBAcquire-releaseFEAT_LSE
00 0 1 1 0 011 LDSETB, LDSETAB, LDSETALB, LDSETLBAcquire-releaseFEAT_LSE
00 0 1 1 0 100 LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLBAcquire-releaseFEAT_LSE
00 0 1 1 0 101 LDSMINB, LDSMINAB, LDSMINALB, LDSMINLBAcquire-releaseFEAT_LSE
00 0 1 1 0 110 LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLBAcquire-releaseFEAT_LSE
00 0 1 1 0 111 LDUMINB, LDUMINAB, LDUMINALB, LDUMINLBAcquire-releaseFEAT_LSE
00 0 1 1 1 000 SWPB, SWPAB, SWPALB, SWPLBSWPALBFEAT_LSE
00 0 1 1 1 001 RCWCLR, RCWCLRA, RCWCLRL, RCWCLRALRCWCLRALFEAT_THE
00 0 1 1 1 010 RCWSWP, RCWSWPA, RCWSWPL, RCWSWPALRCWSWPALFEAT_THE
00 0 1 1 1 011 RCWSET, RCWSETA, RCWSETL, RCWSETALRCWSETALFEAT_THE
01 0 0 0 0 000 LDADDH, LDADDAH, LDADDALH, LDADDLHNo memory orderingFEAT_LSE
01 0 0 0 0 001 LDCLRH, LDCLRAH, LDCLRALH, LDCLRLHNo memory orderingFEAT_LSE
01 0 0 0 0 010 LDEORH, LDEORAH, LDEORALH, LDEORLHNo memory orderingFEAT_LSE
01 0 0 0 0 011 LDSETH, LDSETAH, LDSETALH, LDSETLHNo memory orderingFEAT_LSE
01 0 0 0 0 100 LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLHNo memory orderingFEAT_LSE
01 0 0 0 0 101 LDSMINH, LDSMINAH, LDSMINALH, LDSMINLHNo memory orderingFEAT_LSE
01 0 0 0 0 110 LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLHNo memory orderingFEAT_LSE
01 0 0 0 0 111 LDUMINH, LDUMINAH, LDUMINALH, LDUMINLHNo memory orderingFEAT_LSE
01 0 0 0 1 000 SWPH, SWPAH, SWPALH, SWPLHSWPHFEAT_LSE
01 0 0 0 1 001 RCWSCLR, RCWSCLRA, RCWSCLRL, RCWSCLRALRCWSCLRFEAT_THE
01 0 0 0 1 010 RCWSSWP, RCWSSWPA, RCWSSWPL, RCWSSWPALRCWSSWPFEAT_THE
01 0 0 0 1 011 RCWSSET, RCWSSETA, RCWSSETL, RCWSSETALRCWSSETFEAT_THE
01 0 0 1 0 000 LDADDH, LDADDAH, LDADDALH, LDADDLHReleaseFEAT_LSE
01 0 0 1 0 001 LDCLRH, LDCLRAH, LDCLRALH, LDCLRLHReleaseFEAT_LSE
01 0 0 1 0 010 LDEORH, LDEORAH, LDEORALH, LDEORLHReleaseFEAT_LSE
01 0 0 1 0 011 LDSETH, LDSETAH, LDSETALH, LDSETLHReleaseFEAT_LSE
01 0 0 1 0 100 LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLHReleaseFEAT_LSE
01 0 0 1 0 101 LDSMINH, LDSMINAH, LDSMINALH, LDSMINLHReleaseFEAT_LSE
01 0 0 1 0 110 LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLHReleaseFEAT_LSE
01 0 0 1 0 111 LDUMINH, LDUMINAH, LDUMINALH, LDUMINLHReleaseFEAT_LSE
01 0 0 1 1 000 SWPH, SWPAH, SWPALH, SWPLHSWPLHFEAT_LSE
01 0 0 1 1 001 RCWSCLR, RCWSCLRA, RCWSCLRL, RCWSCLRALRCWSCLRLFEAT_THE
01 0 0 1 1 010 RCWSSWP, RCWSSWPA, RCWSSWPL, RCWSSWPALRCWSSWPLFEAT_THE
01 0 0 1 1 011 RCWSSET, RCWSSETA, RCWSSETL, RCWSSETALRCWSSETLFEAT_THE
01 0 1 0 0 000 LDADDH, LDADDAH, LDADDALH, LDADDLHAcquireFEAT_LSE
01 0 1 0 0 001 LDCLRH, LDCLRAH, LDCLRALH, LDCLRLHAcquireFEAT_LSE
01 0 1 0 0 010 LDEORH, LDEORAH, LDEORALH, LDEORLHAcquireFEAT_LSE
01 0 1 0 0 011 LDSETH, LDSETAH, LDSETALH, LDSETLHAcquireFEAT_LSE
01 0 1 0 0 100 LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLHAcquireFEAT_LSE
01 0 1 0 0 101 LDSMINH, LDSMINAH, LDSMINALH, LDSMINLHAcquireFEAT_LSE
01 0 1 0 0 110 LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLHAcquireFEAT_LSE
01 0 1 0 0 111 LDUMINH, LDUMINAH, LDUMINALH, LDUMINLHAcquireFEAT_LSE
01 0 1 0 1 000 SWPH, SWPAH, SWPALH, SWPLHSWPAHFEAT_LSE
01 0 1 0 1 001 RCWSCLR, RCWSCLRA, RCWSCLRL, RCWSCLRALRCWSCLRAFEAT_THE
01 0 1 0 1 010 RCWSSWP, RCWSSWPA, RCWSSWPL, RCWSSWPALRCWSSWPAFEAT_THE
01 0 1 0 1 011 RCWSSET, RCWSSETA, RCWSSETL, RCWSSETALRCWSSETAFEAT_THE
01 0 1 0 1 100 LDAPRHFEAT_LRCPC
01 0 1 1 0 000 LDADDH, LDADDAH, LDADDALH, LDADDLHAcquire-releaseFEAT_LSE
01 0 1 1 0 001 LDCLRH, LDCLRAH, LDCLRALH, LDCLRLHAcquire-releaseFEAT_LSE
01 0 1 1 0 010 LDEORH, LDEORAH, LDEORALH, LDEORLHAcquire-releaseFEAT_LSE
01 0 1 1 0 011 LDSETH, LDSETAH, LDSETALH, LDSETLHAcquire-releaseFEAT_LSE
01 0 1 1 0 100 LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLHAcquire-releaseFEAT_LSE
01 0 1 1 0 101 LDSMINH, LDSMINAH, LDSMINALH, LDSMINLHAcquire-releaseFEAT_LSE
01 0 1 1 0 110 LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLHAcquire-releaseFEAT_LSE
01 0 1 1 0 111 LDUMINH, LDUMINAH, LDUMINALH, LDUMINLHAcquire-releaseFEAT_LSE
01 0 1 1 1 000 SWPH, SWPAH, SWPALH, SWPLHSWPALHFEAT_LSE
01 0 1 1 1 001 RCWSCLR, RCWSCLRA, RCWSCLRL, RCWSCLRALRCWSCLRALFEAT_THE
01 0 1 1 1 010 RCWSSWP, RCWSSWPA, RCWSSWPL, RCWSSWPALRCWSSWPALFEAT_THE
01 0 1 1 1 011 RCWSSET, RCWSSETA, RCWSSETL, RCWSSETALRCWSSETALFEAT_THE
10 0 1 001 UNALLOCATED-
10 0 1 01x UNALLOCATED-
10 0 0 1 101 UNALLOCATED-
10 0 0 0 0 000 LDADD, LDADDA, LDADDAL, LDADDL32-bit no memory orderingFEAT_LSE
10 0 0 0 0 001 LDCLR, LDCLRA, LDCLRAL, LDCLRL32-bit no memory orderingFEAT_LSE
10 0 0 0 0 010 LDEOR, LDEORA, LDEORAL, LDEORL32-bit no memory orderingFEAT_LSE
10 0 0 0 0 011 LDSET, LDSETA, LDSETAL, LDSETL32-bit no memory orderingFEAT_LSE
10 0 0 0 0 100 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL32-bit no memory orderingFEAT_LSE
10 0 0 0 0 101 LDSMIN, LDSMINA, LDSMINAL, LDSMINL32-bit no memory orderingFEAT_LSE
10 0 0 0 0 110 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL32-bit no memory orderingFEAT_LSE
10 0 0 0 0 111 LDUMIN, LDUMINA, LDUMINAL, LDUMINL32-bit no memory orderingFEAT_LSE
10 0 0 0 1 000 SWP, SWPA, SWPAL, SWPL32-bit SWPFEAT_LSE
10 0 0 1 0 000 LDADD, LDADDA, LDADDAL, LDADDL32-bit releaseFEAT_LSE
10 0 0 1 0 001 LDCLR, LDCLRA, LDCLRAL, LDCLRL32-bit releaseFEAT_LSE
10 0 0 1 0 010 LDEOR, LDEORA, LDEORAL, LDEORL32-bit releaseFEAT_LSE
10 0 0 1 0 011 LDSET, LDSETA, LDSETAL, LDSETL32-bit releaseFEAT_LSE
10 0 0 1 0 100 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL32-bit releaseFEAT_LSE
10 0 0 1 0 101 LDSMIN, LDSMINA, LDSMINAL, LDSMINL32-bit releaseFEAT_LSE
10 0 0 1 0 110 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL32-bit releaseFEAT_LSE
10 0 0 1 0 111 LDUMIN, LDUMINA, LDUMINAL, LDUMINL32-bit releaseFEAT_LSE
10 0 0 1 1 000 SWP, SWPA, SWPAL, SWPL32-bit SWPLFEAT_LSE
10 0 1 0 0 000 LDADD, LDADDA, LDADDAL, LDADDL32-bit acquireFEAT_LSE
10 0 1 0 0 001 LDCLR, LDCLRA, LDCLRAL, LDCLRL32-bit acquireFEAT_LSE
10 0 1 0 0 010 LDEOR, LDEORA, LDEORAL, LDEORL32-bit acquireFEAT_LSE
10 0 1 0 0 011 LDSET, LDSETA, LDSETAL, LDSETL32-bit acquireFEAT_LSE
10 0 1 0 0 100 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL32-bit acquireFEAT_LSE
10 0 1 0 0 101 LDSMIN, LDSMINA, LDSMINAL, LDSMINL32-bit acquireFEAT_LSE
10 0 1 0 0 110 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL32-bit acquireFEAT_LSE
10 0 1 0 0 111 LDUMIN, LDUMINA, LDUMINAL, LDUMINL32-bit acquireFEAT_LSE
10 0 1 0 1 000 SWP, SWPA, SWPAL, SWPL32-bit SWPAFEAT_LSE
10 0 1 0 1 100 LDAPR32-bitFEAT_LRCPC
10 0 1 1 0 000 LDADD, LDADDA, LDADDAL, LDADDL32-bit acquire-releaseFEAT_LSE
10 0 1 1 0 001 LDCLR, LDCLRA, LDCLRAL, LDCLRL32-bit acquire-releaseFEAT_LSE
10 0 1 1 0 010 LDEOR, LDEORA, LDEORAL, LDEORL32-bit acquire-releaseFEAT_LSE
10 0 1 1 0 011 LDSET, LDSETA, LDSETAL, LDSETL32-bit acquire-releaseFEAT_LSE
10 0 1 1 0 100 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL32-bit acquire-releaseFEAT_LSE
10 0 1 1 0 101 LDSMIN, LDSMINA, LDSMINAL, LDSMINL32-bit acquire-releaseFEAT_LSE
10 0 1 1 0 110 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL32-bit acquire-releaseFEAT_LSE
10 0 1 1 0 111 LDUMIN, LDUMINA, LDUMINAL, LDUMINL32-bit acquire-releaseFEAT_LSE
10 0 1 1 1 000 SWP, SWPA, SWPAL, SWPL32-bit SWPALFEAT_LSE
11 0 0 0 0 000 LDADD, LDADDA, LDADDAL, LDADDL64-bit no memory orderingFEAT_LSE
11 0 0 0 0 001 LDCLR, LDCLRA, LDCLRAL, LDCLRL64-bit no memory orderingFEAT_LSE
11 0 0 0 0 010 LDEOR, LDEORA, LDEORAL, LDEORL64-bit no memory orderingFEAT_LSE
11 0 0 0 0 011 LDSET, LDSETA, LDSETAL, LDSETL64-bit no memory orderingFEAT_LSE
11 0 0 0 0 100 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL64-bit no memory orderingFEAT_LSE
11 0 0 0 0 101 LDSMIN, LDSMINA, LDSMINAL, LDSMINL64-bit no memory orderingFEAT_LSE
11 0 0 0 0 110 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL64-bit no memory orderingFEAT_LSE
11 0 0 0 0 111 LDUMIN, LDUMINA, LDUMINAL, LDUMINL64-bit no memory orderingFEAT_LSE
11 0 0 0 1 000 SWP, SWPA, SWPAL, SWPL64-bit SWPFEAT_LSE
11 0 0 0 1 010 ST64BV0FEAT_LS64_ACCDATA
11 0 0 0 1 011 ST64BVFEAT_LS64_V
11 0 0 0 0xxxx 1 x01 UNALLOCATED-
11 0 0 0 10xxx 1 x01 UNALLOCATED-
11 0 0 0 110xx 1 x01 UNALLOCATED-
11 0 0 0 1110x 1 x01 UNALLOCATED-
11 0 0 0 11110 1 x01 UNALLOCATED-
11 0 0 0 11111 1 001 ST64BFEAT_LS64
11 0 0 0 11111 1 101 LD64BFEAT_LS64
11 0 0 1 0 000 LDADD, LDADDA, LDADDAL, LDADDL64-bit releaseFEAT_LSE
11 0 0 1 0 001 LDCLR, LDCLRA, LDCLRAL, LDCLRL64-bit releaseFEAT_LSE
11 0 0 1 0 010 LDEOR, LDEORA, LDEORAL, LDEORL64-bit releaseFEAT_LSE
11 0 0 1 0 011 LDSET, LDSETA, LDSETAL, LDSETL64-bit releaseFEAT_LSE
11 0 0 1 0 100 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL64-bit releaseFEAT_LSE
11 0 0 1 0 101 LDSMIN, LDSMINA, LDSMINAL, LDSMINL64-bit releaseFEAT_LSE
11 0 0 1 0 110 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL64-bit releaseFEAT_LSE
11 0 0 1 0 111 LDUMIN, LDUMINA, LDUMINAL, LDUMINL64-bit releaseFEAT_LSE
11 0 0 1 1 000 SWP, SWPA, SWPAL, SWPL64-bit SWPLFEAT_LSE
11 0 0 1 1 001 UNALLOCATED-
11 0 0 1 1 01x UNALLOCATED-
11 0 1 1 001 UNALLOCATED-
11 0 1 1 01x UNALLOCATED-
11 0 1 0 0 000 LDADD, LDADDA, LDADDAL, LDADDL64-bit acquireFEAT_LSE
11 0 1 0 0 001 LDCLR, LDCLRA, LDCLRAL, LDCLRL64-bit acquireFEAT_LSE
11 0 1 0 0 010 LDEOR, LDEORA, LDEORAL, LDEORL64-bit acquireFEAT_LSE
11 0 1 0 0 011 LDSET, LDSETA, LDSETAL, LDSETL64-bit acquireFEAT_LSE
11 0 1 0 0 100 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL64-bit acquireFEAT_LSE
11 0 1 0 0 101 LDSMIN, LDSMINA, LDSMINAL, LDSMINL64-bit acquireFEAT_LSE
11 0 1 0 0 110 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL64-bit acquireFEAT_LSE
11 0 1 0 0 111 LDUMIN, LDUMINA, LDUMINAL, LDUMINL64-bit acquireFEAT_LSE
11 0 1 0 1 000 SWP, SWPA, SWPAL, SWPL64-bit SWPAFEAT_LSE
11 0 1 0 1 100 LDAPR64-bitFEAT_LRCPC
11 0 1 0 1 101 UNALLOCATED-
11 0 1 1 0 000 LDADD, LDADDA, LDADDAL, LDADDL64-bit acquire-releaseFEAT_LSE
11 0 1 1 0 001 LDCLR, LDCLRA, LDCLRAL, LDCLRL64-bit acquire-releaseFEAT_LSE
11 0 1 1 0 010 LDEOR, LDEORA, LDEORAL, LDEORL64-bit acquire-releaseFEAT_LSE
11 0 1 1 0 011 LDSET, LDSETA, LDSETAL, LDSETL64-bit acquire-releaseFEAT_LSE
11 0 1 1 0 100 LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL64-bit acquire-releaseFEAT_LSE
11 0 1 1 0 101 LDSMIN, LDSMINA, LDSMINAL, LDSMINL64-bit acquire-releaseFEAT_LSE
11 0 1 1 0 110 LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL64-bit acquire-releaseFEAT_LSE
11 0 1 1 0 111 LDUMIN, LDUMINA, LDUMINAL, LDUMINL64-bit acquire-releaseFEAT_LSE
11 0 1 1 1 000 SWP, SWPA, SWPAL, SWPL64-bit SWPALFEAT_LSE

Load/store register (register offset)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
size111VR00opc1RmoptionS10RnRt
Decode fields Instruction Details Feature
size VR opc option Rt
00 0 00 != 011 STRB (register)Extended register-
00 0 00 011 STRB (register)Shifted register-
00 0 01 != 011 LDRB (register)Extended register-
00 0 01 011 LDRB (register)Shifted register-
00 0 10 != 011 LDRSB (register)64-bit with extended register offset-
00 0 10 011 LDRSB (register)64-bit with shifted register offset-
00 0 11 != 011 LDRSB (register)32-bit with extended register offset-
00 0 11 011 LDRSB (register)32-bit with shifted register offset-
00 1 00 != 011 STR (register, SIMD&FP)8-bit-
00 1 00 011 STR (register, SIMD&FP)8-bit-
00 1 01 != 011 LDR (register, SIMD&FP)8-bit-
00 1 01 011 LDR (register, SIMD&FP)8-bit-
00 1 10 STR (register, SIMD&FP)128-bit-
00 1 11 LDR (register, SIMD&FP)128-bit-
01 0 00 STRH (register)-
01 0 01 LDRH (register)-
01 0 10 LDRSH (register)64-bit-
01 0 11 LDRSH (register)32-bit-
01 1 00 STR (register, SIMD&FP)16-bit-
01 1 01 LDR (register, SIMD&FP)16-bit-
01 1 1x UNALLOCATED-
1x 0 11 UNALLOCATED-
1x 1 1x UNALLOCATED-
10 0 00 STR (register)32-bit-
10 0 01 LDR (register)32-bit-
10 0 10 LDRSW (register)-
10 1 00 STR (register, SIMD&FP)32-bit-
10 1 01 LDR (register, SIMD&FP)32-bit-
11 0 00 STR (register)64-bit-
11 0 01 LDR (register)64-bit-
11 0 10 x1x != 11xxx PRFM (register)-
11 0 10 x1x 11xxx RPRFMFEAT_RPRFM
11 0 10 x0x UNALLOCATED-
11 1 00 STR (register, SIMD&FP)64-bit-
11 1 01 LDR (register, SIMD&FP)64-bit-

Load/store register (pac)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
size111VR00MS1imm9W1RnRt
Decode fields Instruction Details Feature
size VR M W
0x UNALLOCATED-
10 UNALLOCATED-
11 0 0 0 LDRAA, LDRABKey A, offsetFEAT_PAuth
11 0 0 1 LDRAA, LDRABKey A, pre-indexedFEAT_PAuth
11 0 1 0 LDRAA, LDRABKey B, offsetFEAT_PAuth
11 0 1 1 LDRAA, LDRABKey B, pre-indexedFEAT_PAuth
11 1 UNALLOCATED-

Load/store register (unsigned immediate)

These instructions are under Loads and Stores.

313029282726252423222120191817161514131211109876543210
size111VR01opcimm12RnRt
Decode fields Instruction Details
size VR opc
00 0 00 STRB (immediate)
00 0 01 LDRB (immediate)
00 0 10 LDRSB (immediate)64-bit
00 0 11 LDRSB (immediate)32-bit
00 1 00 STR (immediate, SIMD&FP)8-bit
00 1 01 LDR (immediate, SIMD&FP)8-bit
00 1 10 STR (immediate, SIMD&FP)128-bit
00 1 11 LDR (immediate, SIMD&FP)128-bit
01 0 00 STRH (immediate)
01 0 01 LDRH (immediate)
01 0 10 LDRSH (immediate)64-bit
01 0 11 LDRSH (immediate)32-bit
01 1 00 STR (immediate, SIMD&FP)16-bit
01 1 01 LDR (immediate, SIMD&FP)16-bit
01 1 1x UNALLOCATED
1x 0 11 UNALLOCATED
1x 1 1x UNALLOCATED
10 0 00 STR (immediate)32-bit
10 0 01 LDR (immediate)32-bit
10 0 10 LDRSW (immediate)
10 1 00 STR (immediate, SIMD&FP)32-bit
10 1 01 LDR (immediate, SIMD&FP)32-bit
11 0 00 STR (immediate)64-bit
11 0 01 LDR (immediate)64-bit
11 0 10 PRFM (immediate)
11 1 00 STR (immediate, SIMD&FP)64-bit
11 1 01 LDR (immediate, SIMD&FP)64-bit

Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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