ADR

Compute vector address

Optionally sign or zero-extend the least significant 32-bits of each element from a vector of offsets or indices in the second source vector, scale each index by 2, 4 or 8, add to a vector of base addresses from the first source vector, and place the resulting addresses in the destination vector. This instruction is unpredicated.

This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.

It has encodings from 3 classes: Packed offsets , Unpacked 32-bit signed offsets and Unpacked 32-bit unsigned offsets

Packed offsets

if !IsFeatureImplemented(FEAT_SVE) then UNDEFINED; constant integer esize = 32 << UInt(sz); constant integer n = UInt(Zn); constant integer m = UInt(Zm); constant integer d = UInt(Zd); constant integer osize = esize; constant boolean unsigned = TRUE; constant integer mbytes = 1 << UInt(msz);

Unpacked 32-bit signed offsets

if !IsFeatureImplemented(FEAT_SVE) then UNDEFINED; constant integer esize = 64; constant integer n = UInt(Zn); constant integer m = UInt(Zm); constant integer d = UInt(Zd); constant integer osize = 32; constant boolean unsigned = FALSE; constant integer mbytes = 1 << UInt(msz);

Unpacked 32-bit unsigned offsets

if !IsFeatureImplemented(FEAT_SVE) then UNDEFINED; constant integer esize = 64; constant integer n = UInt(Zn); constant integer m = UInt(Zm); constant integer d = UInt(Zd); constant integer osize = 32; constant boolean unsigned = TRUE; constant integer mbytes = 1 << UInt(msz);