AESD

AES single round decryption.

Advanced SIMD
(FEAT_AES)

313029282726252423222120191817161514131211109876543210
0100111000101000010110RnRd
sizeD

AESD <Vd>.16B, <Vn>.16B

integer d = UInt(Rd); integer n = UInt(Rn); if !IsFeatureImplemented(FEAT_AES) then UNDEFINED;

Assembler Symbols

<Vd>

Is the name of the SIMD&FP source and destination register, encoded in the "Rd" field.

<Vn>

Is the name of the second SIMD&FP source register, encoded in the "Rn" field.

Operation

AArch64.CheckFPAdvSIMDEnabled(); bits(128) operand1 = V[d, 128]; bits(128) operand2 = V[n, 128]; bits(128) result; result = operand1 EOR operand2; result = AESInvSubBytes(AESInvShiftRows(result)); V[d, 128] = result;

Operational information

If PSTATE.DIT is 1:


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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