AESIMC

AES inverse mix columns

The AESIMC instruction reads a 16-byte state array from each 128-bit segment of the source register, and performs a single round of the InvMixColumns() transformation on each state array in accordance with the AES standard. Each updated state array is destructively placed in the corresponding segment of the first source vector. This instruction is unpredicated.

ID_AA64ZFR0_EL1.AES indicates whether this instruction is implemented.

This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.

SVE2
(FEAT_SVE_AES)

313029282726252423222120191817161514131211109876543210
010001010010000011100100000Zdn
size<1>size<0>

AESIMC <Zdn>.B, <Zdn>.B

if !IsFeatureImplemented(FEAT_SVE) || !IsFeatureImplemented(FEAT_SVE_AES) then UNDEFINED; constant integer dn = UInt(Zdn);

Assembler Symbols

<Zdn>

Is the name of the source and destination scalable vector register, encoded in the "Zdn" field.

Operation

CheckNonStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer segments = VL DIV 128; constant bits(VL) operand = Z[dn, VL]; bits(VL) result; for s = 0 to segments-1 Elem[result, s, 128] = AESInvMixColumns(Elem[operand, s, 128]); Z[dn, VL] = result;

Operational information

If PSTATE.DIT is 1:


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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