Multi-vector floating-point convert from 8-bit floating-point to BFloat16 (in-order)
Convert each 8-bit floating-point element of the source vector to BFloat16 while downscaling the value, and place the results in the corresponding 16-bit elements of the destination vectors. BF1CVT scales the values by 2-UInt(FPMR.LSCALE[5:0]). BF2CVT scales the values by 2-UInt(FPMR.LSCALE2[5:0]). The 8-bit floating-point encoding format for BF1CVT is selected by FPMR.F8S1. The 8-bit floating-point encoding format for BF2CVT is selected by FPMR.F8S2.
This instruction is unpredicated.
It has encodings from 2 classes: BF1CVT and BF2CVT
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | Zn | Zd | 0 | |||||||
| L | |||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SME2) || !IsFeatureImplemented(FEAT_FP8) then UNDEFINED; constant integer n = UInt(Zn); constant integer d = UInt(Zd: '0'); constant boolean issrc2 = FALSE;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | Zn | Zd | 0 | |||||||
| L | |||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SME2) || !IsFeatureImplemented(FEAT_FP8) then UNDEFINED; constant integer n = UInt(Zn); constant integer d = UInt(Zd: '0'); constant boolean issrc2 = TRUE;
| <Zd1> |
Is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 2. |
| <Zd2> |
Is the name of the second scalable vector register of the destination multi-vector group, encoded as "Zd" times 2 plus 1. |
| <Zn> |
Is the name of the source scalable vector register, encoded in the "Zn" field. |
CheckFPMREnabled(); CheckStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV 8; constant bits(VL) operand = Z[n, VL]; bits(2*VL) result; for e = 0 to elements-1 constant bits(8) element = Elem[operand, e, 8]; Elem[result, e, 16] = FP8ConvertBF(element, issrc2, FPCR, FPMR); Z[d+0, VL] = result<VL-1:0>; Z[d+1, VL] = result<2*VL-1:VL>;
Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45
Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.