BFMUL (vectors, predicated)

Multiply active BFloat16 elements of the second source vector to corresponding elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.

SVE2
(FEAT_SVE_B16B16)

if !IsFeatureImplemented(FEAT_SVE_B16B16) then UNDEFINED; constant integer g = UInt(Pg); constant integer dn = UInt(Zdn); constant integer m = UInt(Zm);

Assembler Symbols

<Zdn>

Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field.

<Pg>	Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Zm>	Is the name of the second source scalable vector register, encoded in the "Zm" field.

Operation

CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV 16; constant bits(PL) mask = P[g, PL]; constant bits(VL) operand1 = Z[dn, VL]; constant bits(VL) operand2 = if AnyActiveElement(mask, 16) then Z[m, VL] else Zeros(VL); bits(VL) result; for e = 0 to elements-1 constant bits(16) element1 = Elem[operand1, e, 16]; if ActivePredicateElement(mask, e, 16) then constant bits(16) element2 = Elem[operand2, e, 16]; Elem[result, e, 16] = BFMul(element1, element2, FPCR); else Elem[result, e, 16] = element1; Z[dn, VL] = result;

Operational information

This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is constrained unpredictable:

The MOVPRFX can be predicated or unpredicated.
A predicated MOVPRFX must use the same governing predicate register as this instruction.
A predicated MOVPRFX must use the larger of the destination element size and first source element size in the preferred disassembly of this instruction.
The MOVPRFX must specify the same destination register as this instruction.
The destination register must not refer to architectural register state referenced by any other source operand register of this instruction.

Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	1	1	0	0	1	0	1	0	0	0	0	0	0	1	0	1	0	0	Pg			Zm					Zdn
								size<1>	size<0>