EOR (shifted register)

Bitwise Exclusive-OR (shifted register) performs a bitwise exclusive-OR of a register value and an optionally-shifted register value, and writes the result to the destination register.

313029282726252423222120191817161514131211109876543210
sf1001010shift0Rmimm6RnRd
opcN

32-bit (sf == 0)

EOR <Wd>, <Wn>, <Wm>{, <shift> #<amount>}

64-bit (sf == 1)

EOR <Xd>, <Xn>, <Xm>{, <shift> #<amount>}

if sf == '0' && imm6<5> == '1' then UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); constant integer datasize = 32 << UInt(sf); ShiftType shift_type = DecodeShift(shift); integer shift_amount = UInt(imm6);

Assembler Symbols

<Wd>

Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.

<Wn>

Is the 32-bit name of the first general-purpose source register, encoded in the "Rn" field.

<Wm>

Is the 32-bit name of the second general-purpose source register, encoded in the "Rm" field.

<shift>

Is the optional shift to be applied to the final source, defaulting to LSL and encoded in shift:

shift <shift>
00 LSL
01 LSR
10 ASR
11 ROR
<amount>

For the 32-bit variant: is the shift amount, in the range 0 to 31, defaulting to 0 and encoded in the "imm6" field.

For the 64-bit variant: is the shift amount, in the range 0 to 63, defaulting to 0 and encoded in the "imm6" field,

<Xd>

Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.

<Xn>

Is the 64-bit name of the first general-purpose source register, encoded in the "Rn" field.

<Xm>

Is the 64-bit name of the second general-purpose source register, encoded in the "Rm" field.

Operation

bits(datasize) operand1 = X[n, datasize]; bits(datasize) operand2 = ShiftReg(m, shift_type, shift_amount, datasize); X[d, datasize] = operand1 EOR operand2;

Operational information

If PSTATE.DIT is 1:


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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