EORQV

Bitwise exclusive OR reduction of quadword vector segments

Bitwise exclusive OR of the same element numbers from each 128-bit source vector segment, placing each result into the corresponding element number of the 128-bit SIMD&FP destination register. Inactive elements in the source vector are treated as all zeros.

SVE2
(FEAT_SVE2p1)

313029282726252423222120191817161514131211109876543210
00000100size011101001PgZnVd

EORQV <Vd>.<T>, <Pg>, <Zn>.<Tb>

if !IsFeatureImplemented(FEAT_SVE2p1) && !IsFeatureImplemented(FEAT_SME2p1) then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer g = UInt(Pg); constant integer n = UInt(Zn); constant integer d = UInt(Vd);

Assembler Symbols

<Vd>

Is the name of the destination SIMD&FP register, encoded in the "Vd" field.

<T>

Is an arrangement specifier, encoded in size:

size <T>
00 16B
01 8H
10 4S
11 2D
<Pg>

Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Zn>

Is the name of the source scalable vector register, encoded in the "Zn" field.

<Tb>

Is the size specifier, encoded in size:

size <Tb>
00 B
01 H
10 S
11 D

Operation

CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer segments = VL DIV 128; constant integer elempersegment = 128 DIV esize; constant bits(PL) mask = P[g, PL]; constant bits(VL) operand = if AnyActiveElement(mask, esize) then Z[n, VL] else Zeros(VL); bits(128) result = Zeros(128); bits(128) stmp = Zeros(128); bits(esize) dtmp; for e = 0 to elempersegment-1 dtmp = Zeros(esize); for s = 0 to segments-1 if ActivePredicateElement(mask, s * elempersegment + e, esize) then stmp = Elem[operand, s, 128]; dtmp = dtmp EOR Elem[stmp, e, esize]; Elem[result, e, esize] = dtmp<esize-1:0>; V[d, 128] = result;

Operational information

If PSTATE.DIT is 1:


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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