EXT

Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.

The following figure shows an example of the operation of EXT doubleword operation for Q = 0 and imm4<2:0> = 3.
EXT doubleword operation for Q = 0 and imm4<2:0> = 3

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

313029282726252423222120191817161514131211109876543210
0Q101110000Rm0imm40RnRd
op2

EXT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>, #<index>

integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); if Q == '0' && imm4<3> == '1' then UNDEFINED; constant integer datasize = 64 << UInt(Q); constant integer position = 8 * UInt(imm4);

Assembler Symbols

<Vd>

Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<T>

Is an arrangement specifier, encoded in Q:

Q <T>
0 8B
1 16B
<Vn>

Is the name of the first SIMD&FP source register, encoded in the "Rn" field.

<Vm>

Is the name of the second SIMD&FP source register, encoded in the "Rm" field.

<index>

Is the lowest numbered byte element to be extracted, encoded in Q:imm4:

Q imm4<3> <index>
0 0 UInt(imm4<2:0>)
0 1 RESERVED
1 x UInt(imm4)

Operation

CheckFPAdvSIMDEnabled64(); bits(datasize) hi = V[m, datasize]; bits(datasize) lo = V[n, datasize]; bits(datasize*2) concat = hi:lo; V[d, datasize] = concat<(position+datasize)-1:position>;

Operational information

If PSTATE.DIT is 1:


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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