Floating-point Add Pair of elements (scalar). This instruction adds two floating-point vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.
This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
It has encodings from 2 classes: Half-precision and Single-precision and double-precision
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | Rn | Rd | ||||||||
| U | sz | opcode | |||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_FP16) then UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); constant integer esize = 16; if sz == '1' then UNDEFINED; constant integer datasize = 32;
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| 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | sz | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | Rn | Rd | ||||||||
| U | opcode | ||||||||||||||||||||||||||||||
integer d = UInt(Rd); integer n = UInt(Rn); constant integer esize = 32 << UInt(sz); constant integer datasize = esize * 2;
| <d> |
Is the number of the SIMD&FP destination register, encoded in the "Rd" field. |
| <Vn> |
Is the name of the SIMD&FP source register, encoded in the "Rn" field. |
| <V> |
Is the destination width specifier,
encoded in
|
| <T> |
Is the source arrangement specifier,
encoded in
|
CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n, datasize]; V[d, esize] = FPReduce(ReduceOp_FADD, operand, esize, FPCR);
Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45
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