FCMEQ (zero)

Floating-point Compare Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

It has encodings from 4 classes: Scalar half precision , Scalar single-precision and double-precision , Vector half precision and Vector single-precision and double-precision

Scalar half precision
(FEAT_FP16)

313029282726252423222120191817161514131211109876543210
0101111011111000110110RnRd
Uaop

FCMEQ <Hd>, <Hn>, #0.0

if !IsFeatureImplemented(FEAT_FP16) then UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); constant integer esize = 16; constant integer datasize = esize; integer elements = 1; CompareOp comparison; case op:U of when '00' comparison = CompareOp_GT; when '01' comparison = CompareOp_GE; when '10' comparison = CompareOp_EQ; when '11' comparison = CompareOp_LE;

Scalar single-precision and double-precision

313029282726252423222120191817161514131211109876543210
010111101sz100000110110RnRd
Uop

FCMEQ <V><d>, <V><n>, #0.0

integer d = UInt(Rd); integer n = UInt(Rn); constant integer esize = 32 << UInt(sz); constant integer datasize = esize; integer elements = 1; CompareOp comparison; case op:U of when '00' comparison = CompareOp_GT; when '01' comparison = CompareOp_GE; when '10' comparison = CompareOp_EQ; when '11' comparison = CompareOp_LE;

Vector half precision
(FEAT_FP16)

313029282726252423222120191817161514131211109876543210
0Q00111011111000110110RnRd
Uaop

FCMEQ <Vd>.<T>, <Vn>.<T>, #0.0

if !IsFeatureImplemented(FEAT_FP16) then UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); constant integer esize = 16; constant integer datasize = 64 << UInt(Q); integer elements = datasize DIV esize; CompareOp comparison; case op:U of when '00' comparison = CompareOp_GT; when '01' comparison = CompareOp_GE; when '10' comparison = CompareOp_EQ; when '11' comparison = CompareOp_LE;

Vector single-precision and double-precision

313029282726252423222120191817161514131211109876543210
0Q0011101sz100000110110RnRd
Uop

FCMEQ <Vd>.<T>, <Vn>.<T>, #0.0

integer d = UInt(Rd); integer n = UInt(Rn); if sz:Q == '10' then UNDEFINED; constant integer esize = 32 << UInt(sz); constant integer datasize = 64 << UInt(Q); integer elements = datasize DIV esize; CompareOp comparison; case op:U of when '00' comparison = CompareOp_GT; when '01' comparison = CompareOp_GE; when '10' comparison = CompareOp_EQ; when '11' comparison = CompareOp_LE;

Assembler Symbols

<Hd>

Is the 16-bit name of the SIMD&FP destination register, encoded in the "Rd" field.

<Hn>

Is the 16-bit name of the SIMD&FP source register, encoded in the "Rn" field.

<V>

Is a width specifier, encoded in sz:

sz <V>
0 S
1 D
<d>

Is the number of the SIMD&FP destination register, encoded in the "Rd" field.

<n>

Is the number of the SIMD&FP source register, encoded in the "Rn" field.

<Vd>

Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<T>

For the half-precision variant: is an arrangement specifier, encoded in Q:

Q <T>
0 4H
1 8H

For the single-precision and double-precision variant: is an arrangement specifier, encoded in sz:Q:

sz Q <T>
0 0 2S
0 1 4S
1 0 RESERVED
1 1 2D
<Vn>

Is the name of the SIMD&FP source register, encoded in the "Rn" field.

Operation

CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n, datasize]; bits(datasize) result; bits(esize) zero = FPZero('0', esize); bits(esize) element; boolean test_passed; for e = 0 to elements-1 element = Elem[operand, e, esize]; case comparison of when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR); when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR); when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR); when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR); when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR); Elem[result, e, esize] = if test_passed then Ones(esize) else Zeros(esize); V[d, datasize] = result;


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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