Multi-vector floating-point convert from half-precision to single-precision (in-order)
Convert to single-precision from half-precision, each element of the source vector, and place the results in the double-width destination elements of the destination vectors.
This instruction follows SME2 floating-point numerical behaviors corresponding to instructions that place their results in one or more SVE Z vectors.
This instruction is unpredicated.
ID_AA64SMFR0_EL1.F16F16 indicates whether this instruction is implemented.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | Zn | Zd | 0 | |||||||
| L | |||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SME_F16F16) then UNDEFINED; constant integer n = UInt(Zn); constant integer d = UInt(Zd:'0');
| <Zd1> |
Is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 2. |
| <Zd2> |
Is the name of the second scalable vector register of the destination multi-vector group, encoded as "Zd" times 2 plus 1. |
| <Zn> |
Is the name of the source scalable vector register, encoded in the "Zn" field. |
CheckStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV 16; constant bits(VL) operand = Z[n, VL]; bits(2*VL) result; for e = 0 to elements-1 constant bits(16) element = Elem[operand, e, 16]; constant bits(32) res = FPConvertSVE(element, FPCR, 32); Elem[result, e, 32] = res; Z[d+0, VL] = result<VL-1:0>; Z[d+1, VL] = result<2*VL-1:VL>;
Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45
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