Multi-vector floating-point convert from half-precision to packed 8-bit floating-point format
Convert each half-precision element of the two source vectors to 8-bit floating-point while scaling the value by 2SInt(FPMR.NSCALE[4:0]), and place the results in the half-width elements of the destination vector. The 8-bit floating-point encoding format is selected by FPMR.F8D.
This instruction is unpredicated.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | Zn | 0 | Zd | |||||||
if !IsFeatureImplemented(FEAT_SME2) || !IsFeatureImplemented(FEAT_FP8) then UNDEFINED; constant integer n = UInt(Zn:'0'); constant integer d = UInt(Zd);
| <Zd> |
Is the name of the destination scalable vector register, encoded in the "Zd" field. |
| <Zn1> |
Is the name of the first scalable vector register of the source multi-vector group, encoded as "Zn" times 2. |
| <Zn2> |
Is the name of the second scalable vector register of the source multi-vector group, encoded as "Zn" times 2 plus 1. |
CheckFPMREnabled(); CheckStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer elements = VL DIV 16; bits(VL) result; constant bits(VL) operand1 = Z[n+0, VL]; constant bits(VL) operand2 = Z[n+1, VL]; for e = 0 to elements-1 constant bits(16) element1 = Elem[operand1, e, 16]; constant bits(16) element2 = Elem[operand2, e, 16]; Elem[result, 0*elements + e, 8] = FPConvertFP8(element1, FPCR, FPMR, 8); Elem[result, 1*elements + e, 8] = FPConvertFP8(element2, FPCR, FPMR, 8); Z[d, VL] = result;
Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45
Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.