FCVTN (half-precision to 8-bit floating-point) -- A64

Half-precision to 8-bit floating-point convert and narrow (vector). This instruction converts half-precision elements of the two source vectors to 8-bit floating-point while scaling the values by 2^{SInt(FPMR.NSCALE[4:0])}, and places the in-order results in the 8-bit elements of the destination vector.

Advanced SIMD
(FEAT_FP8)

if !IsFeatureImplemented(FEAT_FP8) then UNDEFINED; integer n = UInt(Rn); integer m = UInt(Rm); integer d = UInt(Rd); constant integer datasize = if Q == '1' then 128 else 64; constant integer elements = datasize DIV 16;

Assembler Symbols

<Vd>	Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<Ta>

Is an arrangement specifier, encoded in Q:

Q	<Ta>
0	8B
1	16B

<Vn>	Is the name of the first SIMD&FP source register, encoded in the "Rn" field.

<Tb>

Is an arrangement specifier, encoded in Q:

Q	<Tb>
0	4H
1	8H

<Vm>	Is the name of the second SIMD&FP source register, encoded in the "Rm" field.

Operation

CheckFPMREnabled(); CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n, datasize]; bits(datasize) operand2 = V[m, datasize]; bits(datasize) result; for e = 0 to elements-1 Elem[result, 0*elements+e, 8] = FPConvertFP8(Elem[operand1, e, 16], FPCR, FPMR, 8); Elem[result, 1*elements+e, 8] = FPConvertFP8(Elem[operand2, e, 16], FPCR, FPMR, 8); V[d, datasize] = result;

Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	Q	0	0	1	1	1	0	0	1	0	Rm					1	1	1	1	0	1	Rn					Rd
		U						size									opcode