Floating-point fused multiply-add vectors (predicated), writing multiplicand [Zdn = Za + Zdn * Zm]
Multiply the corresponding active floating-point elements of the first and second source vectors and add to elements of the third (addend) vector without intermediate rounding. Destructively place the results in the destination and first source (multiplicand) vector. Inactive elements in the destination vector register remain unmodified.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | size | 1 | Za | 1 | 0 | 0 | Pg | Zm | Zdn | |||||||||||||||
| N | op | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; if size == '00' then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer g = UInt(Pg); constant integer dn = UInt(Zdn); constant integer m = UInt(Zm); constant integer a = UInt(Za); constant boolean op1_neg = FALSE; constant boolean op3_neg = FALSE;
| <Zdn> |
Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field. |
| <T> |
Is the size specifier,
encoded in
|
| <Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
| <Zm> |
Is the name of the second source scalable vector register, encoded in the "Zm" field. |
| <Za> |
Is the name of the third source scalable vector register, encoded in the "Za" field. |
CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; constant bits(PL) mask = P[g, PL]; constant bits(VL) op1 = Z[dn, VL]; constant bits(VL) op2 = if AnyActiveElement(mask, esize) then Z[m, VL] else Zeros(VL); constant bits(VL) op3 = if AnyActiveElement(mask, esize) then Z[a, VL] else Zeros(VL); bits(VL) result; for e = 0 to elements-1 if ActivePredicateElement(mask, e, esize) then constant bits(esize) elem1 = (if op1_neg then FPNeg(Elem[op1, e, esize], FPCR) else Elem[op1, e, esize]); constant bits(esize) elem2 = Elem[op2, e, esize]; constant bits(esize) elem3 = (if op3_neg then FPNeg(Elem[op3, e, esize], FPCR) else Elem[op3, e, esize]); Elem[result, e, esize] = FPMulAdd(elem3, elem1, elem2, FPCR); else Elem[result, e, esize] = Elem[op1, e, esize]; Z[dn, VL] = result;
This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is constrained unpredictable:
Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45
Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.