FMAXNMV

Floating-point Maximum Number across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are floating-point values.

Regardless of the value of FPCR.AH, the behavior is as follows:

• Negative zero compares less than positive zero.
• If one value is numeric and the other is a quiet NaN, the result is the numeric value.
• When FPCR.DN is 0, if either value is a signaling NaN or if both values are NaNs, the result is a quiet NaN.
• When FPCR.DN is 1, if either value is a signaling NaN or if both values are NaNs, the result is Default NaN.

This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

It has encodings from 2 classes: Half-precision and Single-precision

Half-precision
(FEAT_FP16)

if !IsFeatureImplemented(FEAT_FP16) then UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); constant integer esize = 16; constant integer datasize = 64 << UInt(Q);

Single-precision

integer d = UInt(Rd); integer n = UInt(Rn); if sz:Q != '01' then UNDEFINED; // .4S only constant integer esize = 32; constant integer datasize = 64 << UInt(Q);