8-bit floating-point multiply-add long to half-precision (vector). This instruction widens the even-numbered (bottom) or odd-numbered (top) 8-bit elements in the first and second source vectors to half-precision format and multiplies the corresponding elements. The intermediate products are scaled by 2-UInt(FPMR.LSCALE[3:0]), before being destructively added without intermediate rounding to the half-precision elements of the destination vector that overlap with the corresponding 8-bit floating-point elements in the source vectors.
The 8-bit floating-point encoding format for the elements of the first source vector is selected by FPMR.F8S1. The 8-bit floating-point encoding format for the elements of the second source vector is selected by FPMR.F8S2.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | Q | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | Rm | 1 | 1 | 1 | 1 | 1 | 1 | Rn | Rd | ||||||||||||
U | size | opcode |
if !IsFeatureImplemented(FEAT_FP8FMA) then UNDEFINED; integer n = UInt(Rn); integer m = UInt(Rm); integer d = UInt(Rd); constant integer elements = 128 DIV 16; integer sel = UInt(Q);
<Vd> |
Is the name of the SIMD&FP destination register, encoded in the "Rd" field. |
<Vn> |
Is the name of the first SIMD&FP source register, encoded in the "Rn" field. |
<Vm> |
Is the name of the second SIMD&FP source register, encoded in the "Rm" field. |
CheckFPMREnabled(); CheckFPAdvSIMDEnabled64(); bits(128) operand1 = V[n, 128]; bits(128) operand2 = V[m, 128]; bits(128) operand3 = V[d, 128]; bits(128) result; for e = 0 to elements-1 bits(8) element1 = Elem[operand1, 2*e+sel, 8]; bits(8) element2 = Elem[operand2, 2*e+sel, 8]; bits(16) element3 = Elem[operand3, e, 16]; Elem[result, e, 16] = FP8MulAddFP(element3, element1, element2, FPCR, FPMR); V[d, 128] = result;
Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45
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