FMLALLBB, FMLALLBT, FMLALLTB, FMLALLTT (vector)

8-bit floating-point multiply-add long-long to single-precision (vector). This instruction widens the first (bottom bottom), second (bottom top), third (top bottom), or fourth (top top) 8-bit element of each 32-bit container in the first and second source vectors to single-precision format and multiplies the corresponding elements. The intermediate products are scaled by 2-UInt(FPMR.LSCALE), before being destructively added without intermediate rounding to the single-precision elements of the destination vector that overlap with the corresponding 8-bit floating-point elements in the source vectors.

The 8-bit floating-point encoding format for the elements of the first source vector is selected by FPMR.F8S1. The 8-bit floating-point encoding format for the elements of the second source vector is selected by FPMR.F8S2.

Advanced SIMD
(FEAT_FP8FMA)

313029282726252423222120191817161514131211109876543210
0Q0011100x0Rm110001RnRd
Usizeopcode

FMLALLBB (Q == 0 && size == 00)

FMLALLBB <Vd>.4S, <Vn>.16B, <Vm>.16B

FMLALLBT (Q == 0 && size == 01)

FMLALLBT <Vd>.4S, <Vn>.16B, <Vm>.16B

FMLALLTB (Q == 1 && size == 00)

FMLALLTB <Vd>.4S, <Vn>.16B, <Vm>.16B

FMLALLTT (Q == 1 && size == 01)

FMLALLTT <Vd>.4S, <Vn>.16B, <Vm>.16B

if !IsFeatureImplemented(FEAT_FP8FMA) then UNDEFINED; integer n = UInt(Rn); integer m = UInt(Rm); integer d = UInt(Rd); constant integer elements = 128 DIV 32; integer sel = UInt(Q:size<0>);

Assembler Symbols

<Vd>

Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<Vn>

Is the name of the first SIMD&FP source register, encoded in the "Rn" field.

<Vm>

Is the name of the second SIMD&FP source register, encoded in the "Rm" field.

Operation

CheckFPMREnabled(); CheckFPAdvSIMDEnabled64(); bits(128) operand1 = V[n, 128]; bits(128) operand2 = V[m, 128]; bits(128) operand3 = V[d, 128]; bits(128) result; for e = 0 to elements-1 bits(8) element1 = Elem[operand1, 4*e+sel, 8]; bits(8) element2 = Elem[operand2, 4*e+sel, 8]; bits(32) element3 = Elem[operand3, e, 32]; Elem[result, e, 32] = FP8MulAddFP(element3, element1, element2, FPCR, FPMR); V[d, 128] = result;


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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