FMLSL, FMLSL2 (vector)

Floating-point fused Multiply-Subtract Long from accumulator (vector). This instruction negates the half-precision values in the vector of one SIMD&FP register, multiplies these with the corresponding half-precision values in another vector, and accumulates the intermediate product without rounding to the corresponding single-precision vector element of the destination SIMD&FP register.

A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

In Armv8.2 and Armv8.3, this is an OPTIONAL instruction. From Armv8.4, it is mandatory for all implementations to support it.

It has encodings from 2 classes: FMLSL and FMLSL2

FMLSL
(FEAT_FHM)

if !IsFeatureImplemented(FEAT_FHM) then UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); if sz == '1' then UNDEFINED; constant integer esize = 32; constant integer datasize = 64 << UInt(Q); integer elements = datasize DIV esize; boolean sub_op = (S == '1'); integer part = 0;

FMLSL2
(FEAT_FHM)

if !IsFeatureImplemented(FEAT_FHM) then UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn); integer m = UInt(Rm); if sz == '1' then UNDEFINED; constant integer esize = 32; constant integer datasize = 64 << UInt(Q); integer elements = datasize DIV esize; boolean sub_op = (S == '1'); integer part = 1;