Halt instruction. An HLT instruction can generate a Halt Instruction debug event, which causes entry into Debug state.
Within a guarded memory region, while PSTATE.BTYPE != 0b00, a HLT instruction that would cause entry into Debug state will not generate a Branch Target Exception and will cause entry into Debug state as normal. For more information, see PSTATE.BTYPE.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | imm16 | 0 | 0 | 0 | 0 | 0 | |||||||||||||||
| opc | op2 | LL | |||||||||||||||||||||||||||||
HLT #<imm>
if EDSCR.HDE == '0' || !HaltingAllowed() then UNDEFINED; if IsFeatureImplemented(FEAT_BTI) then SetBTypeCompatible(TRUE);
boolean is_async = FALSE; FaultRecord fault = NoFault(); Halt(DebugHalt_HaltInstruction, is_async, fault);
Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45
Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.