INS (general)

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

This instruction is used by the alias MOV (from general).

313029282726252423222120191817161514131211109876543210
01001110000imm5000111RnRd
Qopimm4

INS <Vd>.<Ts>[<index>], <R><n>

integer d = UInt(Rd); integer n = UInt(Rn); constant integer size = LowestSetBit(imm5); if size > 3 then UNDEFINED; constant integer index = UInt(imm5<4:size+1>); constant integer esize = 8 << size;

Assembler Symbols

<Vd>

Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<Ts>

Is an element size specifier, encoded in imm5:

imm5 <Ts>
x0000 RESERVED
xxxx1 B
xxx10 H
xx100 S
x1000 D
<index>

Is the element index encoded in imm5:

imm5 <index>
x0000 RESERVED
xxxx1 UInt(imm5<4:1>)
xxx10 UInt(imm5<4:2>)
xx100 UInt(imm5<4:3>)
x1000 UInt(imm5<4>)
<R>

Is the width specifier for the general-purpose source register, encoded in imm5:

imm5 <R>
x0000 RESERVED
xxxx1 W
xxx10 W
xx100 W
x1000 X
<n>

Is the number [0-30] of the general-purpose source register or ZR (31), encoded in the "Rn" field.

Operation

CheckFPAdvSIMDEnabled64(); bits(esize) element = X[n, esize]; bits(128) result; result = V[d, 128]; Elem[result, index, esize] = element; V[d, 128] = result;

Operational information

If PSTATE.DIT is 1:


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.