Load multiple 3-element structures to three registers. This instruction loads multiple 3-element structures from memory and writes the result to the three SIMD&FP registers, with de-interleaving.
The following figure shows an example of the operation of de-interleaving of a LD3.16 (multiple 3-element structures) instruction:.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
It has encodings from 2 classes: No offset and Post-index
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | Q | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | size | Rn | Rt | |||||||||
| L | opcode | ||||||||||||||||||||||||||||||
integer t = UInt(Rt); integer n = UInt(Rn); integer m = integer UNKNOWN; boolean wback = FALSE; boolean nontemporal = FALSE; boolean tagchecked = wback || n != 31;
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | Q | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | Rm | 0 | 1 | 0 | 0 | size | Rn | Rt | |||||||||||||
| L | opcode | ||||||||||||||||||||||||||||||
integer t = UInt(Rt); integer n = UInt(Rn); integer m = UInt(Rm); boolean wback = TRUE; boolean nontemporal = FALSE; boolean tagchecked = wback || n != 31;
| <Vt> |
Is the name of the first or only SIMD&FP register to be transferred, encoded in the "Rt" field. |
| <T> |
Is an arrangement specifier,
encoded in
|
| <Vt2> |
Is the name of the second SIMD&FP register to be transferred, encoded as "Rt" plus 1 modulo 32. |
| <Vt3> |
Is the name of the third SIMD&FP register to be transferred, encoded as "Rt" plus 2 modulo 32. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
| <imm> |
Is the post-index immediate offset,
encoded in
|
| <Xm> |
Is the 64-bit name of the general-purpose post-index register, excluding XZR, encoded in the "Rm" field. |
constant integer datasize = 64 << UInt(Q); constant integer esize = 8 << UInt(size); integer elements = datasize DIV esize; integer rpt = 1; integer selem = 3; // .1D format only permitted with LD1 & ST1 if size:Q == '110' && selem != 1 then UNDEFINED;
CheckFPAdvSIMDEnabled64(); bits(64) address; bits(64) eaddr; bits(64) offs; bits(datasize) rval; integer tt; constant integer ebytes = esize DIV 8; AccessDescriptor accdesc = CreateAccDescASIMD(MemOp_LOAD, nontemporal, tagchecked); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; offs = Zeros(64); for r = 0 to rpt-1 for e = 0 to elements-1 tt = (t + r) MOD 32; for s = 0 to selem-1 rval = V[tt, datasize]; eaddr = AddressIncrement(address, offs, accdesc); Elem[rval, e, esize] = Mem[eaddr, ebytes, accdesc]; V[tt, datasize] = rval; offs = offs + ebytes; tt = (tt + 1) MOD 32; if wback then if m != 31 then offs = X[m, 64]; address = AddressAdd(address, offs, accdesc); if n == 31 then SP[] = address; else X[n, 64] = address;
If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.
Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45
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