Load-Acquire RCpc Register Halfword derives an address from a base register value, loads a halfword from the derived address in memory, zero-extends it and writes it to a register.
The instruction has memory ordering semantics as described in Load-Acquire, Load-AcquirePC, and Store-Release, except that:
This difference in memory ordering is not described in the pseudocode.
For information about addressing modes, see Load/Store addressing modes.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | (1) | (1) | (1) | (1) | (1) | 1 | 1 | 0 | 0 | 0 | 0 | Rn | Rt | ||||||||
| size | VR | A | R | Rs | o3 | opc | |||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_LRCPC) then UNDEFINED; integer t = UInt(Rt); integer n = UInt(Rn); boolean tagchecked = n != 31;
| <Wt> |
Is the 32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
bits(64) address; bits(16) data; AccessDescriptor accdesc = CreateAccDescLDAcqPC(tagchecked); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; data = Mem[address, 2, accdesc]; X[t, 32] = ZeroExtend(data, 32);
If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.
Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45
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