bits(64) address; bits(datasize) data; constant integer dbytes = datasize DIV 8; AccessDescriptor accdesc = CreateAccDescExLDST(MemOp_LOAD, TRUE, tagchecked); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; // Tell the Exclusives monitors to record a sequence of one or more atomic // memory reads from virtual address range [address, address+dbytes-1]. // The Exclusives monitor will only be set if all the reads are from the // same dbytes-aligned physical address, to allow for the possibility of // an atomicity break if the translation is changed between reads. AArch64.SetExclusiveMonitors(address, dbytes); if rt_unknown then // ConstrainedUNPREDICTABLE case X[t, datasize] = bits(datasize) UNKNOWN; // In this case t = t2 elsif elsize == 32 then // 32-bit load exclusive pair (atomic) data = Mem[address, dbytes, accdesc]; if BigEndian(accdesc.acctype) then X[t, elsize] = data<elsize +: elsize>; X[t2, elsize] = data<0 +: elsize>; else X[t, elsize] = data<0 +: elsize>; X[t2, elsize] = data<elsize +: elsize>; else // elsize == 64 // 64-bit load exclusive pair (not atomic), but must be 128-bit aligned if !IsAligned(address, dbytes) then AArch64.Abort(address, AlignmentFault(accdesc)); bits(64) address2 = AddressIncrement(address, 8, accdesc); X[t, 64] = Mem[address , 8, accdesc]; X[t2, 64] = Mem[address2, 8, accdesc];