Load Tag Multiple reads a naturally aligned block of N Allocation Tags, where the size of N is identified in GMID_EL1.BS, and writes the Allocation Tag read from address A to the destination register at 4*A<7:4>+3:4*A<7:4>. Bits of the destination register not written with an Allocation Tag are set to 0.
This instruction is UNDEFINED at EL0.
This instruction generates an Unchecked access.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | Xn | Xt | ||||||||
| opc | imm9 | op2 | |||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_MTE2) then UNDEFINED; integer t = UInt(Xt); integer n = UInt(Xn);
| <Xt> |
Is the 64-bit name of the general-purpose destination register, encoded in the "Xt" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Xn" field. |
if PSTATE.EL == EL0 then UNDEFINED; bits(64) data = Zeros(64); bits(64) address; if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; integer size = 4 * (2 ^ (UInt(GMID_EL1.BS))); address = Align(address, size); constant integer count = size >> LOG2_TAG_GRANULE; integer index = UInt(address<LOG2_TAG_GRANULE+3:LOG2_TAG_GRANULE>); boolean devstoreunpred = FALSE; AccessDescriptor accdesc = CreateAccDescLDGSTG(MemOp_LOAD, devstoreunpred); for i = 0 to count-1 bits(4) tag = AArch64.MemTag[address, accdesc]; Elem[data, index, 4] = tag; address = AddressIncrement(address, TAG_GRANULE, accdesc); index = index + 1; X[t, 64] = data;
Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45
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