LDR (predicate)

Load predicate register

Load a predicate register from a memory address generated by a 64-bit scalar base, plus an immediate offset in the range -256 to 255 which is multiplied by the current predicate register size in bytes. This instruction is unpredicated.

The load is performed as contiguous byte accesses, each containing 8 consecutive predicate bits in ascending element order, with no endian conversion and no guarantee of single-copy atomicity larger than a byte. However, if alignment is checked, then a general-purpose base register must be aligned to 2 bytes.

For programmer convenience, an assembler must also accept a predicate-as-counter register name for the destination predicate register.

313029282726252423222120191817161514131211109876543210
1000010110imm9h000imm9lRn0Pt

LDR <Pt>, [<Xn|SP>{, #<imm>, MUL VL}]

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer t = UInt(Pt); constant integer n = UInt(Rn); constant integer imm = SInt(imm9h:imm9l);

Assembler Symbols

<Pt>

Is the name of the destination scalable predicate register, encoded in the "Pt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<imm>

Is the optional signed immediate vector offset, in the range -256 to 255, defaulting to 0, encoded in the "imm9h:imm9l" fields.

Operation

CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = PL DIV 8; bits(64) base; constant integer offset = imm * elements; bits(PL) result; constant boolean contiguous = TRUE; constant boolean nontemporal = FALSE; constant boolean tagchecked = n != 31; constant AccessDescriptor accdesc = CreateAccDescSVE(MemOp_LOAD, nontemporal, contiguous, tagchecked); if n == 31 then CheckSPAlignment(); base = SP[]; else base = X[n, 64]; bits(64) addr = AddressAdd(base, offset, accdesc); constant boolean aligned = IsAligned(addr, 2); if !aligned && AlignmentEnforced() then AArch64.Abort(addr, AlignmentFault(accdesc)); for e = 0 to elements-1 Elem[result, e, 8] = AArch64.MemSingle[addr, 1, accdesc, aligned]; addr = AddressIncrement(addr, 1, accdesc); P[t, PL] = result;

Operational information

If FEAT_SVE2 is implemented or FEAT_SME is implemented, then if PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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