LDSETB, LDSETAB, LDSETALB, LDSETLB

Atomic bit set on byte in memory atomically loads an 8-bit byte from memory, performs a bitwise OR with the value held in a register on it, and stores the result back to memory. The value initially loaded from memory is returned in the destination register.

For more information about memory ordering semantics, see Load-Acquire, Store-Release.

For information about addressing modes, see Load/Store addressing modes.

This instruction is used by the alias STSETB, STSETLB.

Integer
(FEAT_LSE)

313029282726252423222120191817161514131211109876543210
00111000AR1Rs001100RnRt
sizeVRo3opc

Acquire (A == 1 && R == 0)

LDSETAB <Ws>, <Wt>, [<Xn|SP>]

Acquire-release (A == 1 && R == 1)

LDSETALB <Ws>, <Wt>, [<Xn|SP>]

No memory ordering (A == 0 && R == 0)

LDSETB <Ws>, <Wt>, [<Xn|SP>]

Release (A == 0 && R == 1)

LDSETLB <Ws>, <Wt>, [<Xn|SP>]

if !IsFeatureImplemented(FEAT_LSE) then UNDEFINED; integer s = UInt(Rs); integer t = UInt(Rt); integer n = UInt(Rn); boolean acquire = A == '1' && Rt != '11111'; boolean release = R == '1'; boolean tagchecked = n != 31;

Assembler Symbols

<Ws>

Is the 32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field.

<Wt>

Is the 32-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

Alias Conditions

AliasIs preferred when
STSETB, STSETLBA == '0' && Rt == '11111'

Operation

bits(64) address; AccessDescriptor accdesc = CreateAccDescAtomicOp(MemAtomicOp_ORR, acquire, release, tagchecked); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; bits(8) comparevalue = bits(8) UNKNOWN; // Irrelevant when not executing CAS bits(8) value = X[s, 8]; bits(8) data = MemAtomic(address, comparevalue, value, accdesc); if t != 31 then X[t, 32] = ZeroExtend(data, 32);

Operational information

If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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