MOV (element)

Move vector element to another vector element. This instruction copies the vector element of the source SIMD&FP register to the specified vector element of the destination SIMD&FP register.

This instruction can insert data into individual elements within a SIMD&FP register without clearing the remaining bits to zero.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

This is an alias of INS (element). This means:

313029282726252423222120191817161514131211109876543210
01101110000imm50imm41RnRd
Qop

MOV <Vd>.<Ts>[<index1>], <Vn>.<Ts>[<index2>]

is equivalent to

INS <Vd>.<Ts>[<index1>], <Vn>.<Ts>[<index2>]

and is always the preferred disassembly.

Assembler Symbols

<Vd>

Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<Ts>

Is an element size specifier, encoded in imm5:

imm5 <Ts>
x0000 RESERVED
xxxx1 B
xxx10 H
xx100 S
x1000 D
<index1>

Is the destination element index encoded in imm5:

imm5 <index1>
x0000 RESERVED
xxxx1 UInt(imm5<4:1>)
xxx10 UInt(imm5<4:2>)
xx100 UInt(imm5<4:3>)
x1000 UInt(imm5<4>)
<Vn>

Is the name of the SIMD&FP source register, encoded in the "Rn" field.

<index2>

Is the source element index encoded in imm5:imm4:

imm5 <index2>
x0000 RESERVED
xxxx1 UInt(imm4)
xxx10 UInt(imm4<3:1>)
xx100 UInt(imm4<3:2>)
x1000 UInt(imm4<3>)
Unspecified bits in "imm4" are ignored but should be set to zero by an assembler.

Operation

The description of INS (element) gives the operational pseudocode for this instruction.

Operational information

If PSTATE.DIT is 1:


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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