MOV (tile to vector, two registers)

Move two ZA tile slices to two vector registers

The instruction operates on two consecutive horizontal or vertical slices within a named ZA tile of the specified element size.

The consecutive slice numbers within the tile are selected starting from the sum of the slice index register and immediate offset, modulo the number of such elements in a vector. The immediate offset is a multiple of 2 in the range 0 to the number of elements in a 128-bit vector segment minus 2.

This instruction is unpredicated.

This is an alias of MOVA (tile to vector, two registers). This means:

It has encodings from 4 classes: 8-bit , 16-bit , 32-bit and 64-bit

8-bit

313029282726252423222120191817161514131211109876543210
1100000000000110VRs00000off3Zd0
size<1>size<0>

MOV { <Zd1>.B-<Zd2>.B }, ZA0<HV>.B[<Ws>, <offs1>:<offs2>]

is equivalent to

MOVA { <Zd1>.B-<Zd2>.B }, ZA0<HV>.B[<Ws>, <offs1>:<offs2>]

and is always the preferred disassembly.

16-bit

313029282726252423222120191817161514131211109876543210
1100000001000110VRs00000ZAnoff2Zd0
size<1>size<0>

MOV { <Zd1>.H-<Zd2>.H }, <ZAn><HV>.H[<Ws>, <offs1>:<offs2>]

is equivalent to

MOVA { <Zd1>.H-<Zd2>.H }, <ZAn><HV>.H[<Ws>, <offs1>:<offs2>]

and is always the preferred disassembly.

32-bit

313029282726252423222120191817161514131211109876543210
1100000010000110VRs00000ZAno1Zd0
size<1>size<0>

MOV { <Zd1>.S-<Zd2>.S }, <ZAn><HV>.S[<Ws>, <offs1>:<offs2>]

is equivalent to

MOVA { <Zd1>.S-<Zd2>.S }, <ZAn><HV>.S[<Ws>, <offs1>:<offs2>]

and is always the preferred disassembly.

64-bit

313029282726252423222120191817161514131211109876543210
1100000011000110VRs00000ZAnZd0
size<1>size<0>

MOV { <Zd1>.D-<Zd2>.D }, <ZAn><HV>.D[<Ws>, <offs1>:<offs2>]

is equivalent to

MOVA { <Zd1>.D-<Zd2>.D }, <ZAn><HV>.D[<Ws>, <offs1>:<offs2>]

and is always the preferred disassembly.

Assembler Symbols

<Zd1>

Is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 2.

<Zd2>

Is the name of the second scalable vector register of the destination multi-vector group, encoded as "Zd" times 2 plus 1.

<ZAn>

For the 16-bit variant: is the name of the ZA tile ZA0-ZA1 to be accessed, encoded in the "ZAn" field.

For the 32-bit variant: is the name of the ZA tile ZA0-ZA3 to be accessed, encoded in the "ZAn" field.

For the 64-bit variant: is the name of the ZA tile ZA0-ZA7 to be accessed, encoded in the "ZAn" field.

<HV>

Is the horizontal or vertical slice indicator, encoded in V:

V <HV>
0 H
1 V
<Ws>

Is the 32-bit name of the slice index register W12-W15, encoded in the "Rs" field.

<offs1>

For the 8-bit variant: is the first slice index offset, encoded as "off3" field times 2.

For the 16-bit variant: is the first slice index offset, encoded as "off2" field times 2.

For the 32-bit variant: is the first slice index offset, encoded as "o1" field times 2.

For the 64-bit variant: is the first slice index offset, with implicit value 0.

<offs2>

For the 8-bit variant: is the second slice index offset, encoded as "off3" field times 2 plus 1.

For the 16-bit variant: is the second slice index offset, encoded as "off2" field times 2 plus 1.

For the 32-bit variant: is the second slice index offset, encoded as "o1" field times 2 plus 1.

For the 64-bit variant: is the second slice index offset, with implicit value 1.

Operation

The description of MOVA (tile to vector, two registers) gives the operational pseudocode for this instruction.

Operational information

If FEAT_SVE2 is implemented or FEAT_SME is implemented, then if PSTATE.DIT is 1:


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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