Move four ZA single-vector groups to four vector registers
The instruction operates on four ZA single-vector groups.
The single-vector group within each quarter of the ZA array is selected by the sum of the vector select register and offset, modulo quarter the number of ZA array vectors.
The vector group symbol VGx4 indicates that the instruction operates on four ZA single-vector groups.
The preferred disassembly syntax uses a 64-bit element size, but an assembler should accept any element size if it is used consistently for all operands. The vector group symbol is preferred for disassembly, but optional in assembler source code.
This instruction is unpredicated.
This is an alias of MOVA (array to vector, four registers). This means:
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | Rv | 0 | 1 | 1 | 0 | 0 | off3 | Zd | 0 | 0 |
MOV { <Zd1>.D-<Zd4>.D }, ZA.D[<Wv>, <offs>{, VGx4}]
is equivalent to
MOVA { <Zd1>.D-<Zd4>.D }, ZA.D[<Wv>, <offs>{, VGx4}]
and is always the preferred disassembly.
<Zd1> |
Is the name of the first scalable vector register of the destination multi-vector group, encoded as "Zd" times 4. |
<Zd4> |
Is the name of the fourth scalable vector register of the destination multi-vector group, encoded as "Zd" times 4 plus 3. |
<Wv> |
Is the 32-bit name of the vector select register W8-W11, encoded in the "Rv" field. |
<offs> |
Is the vector select offset, in the range 0 to 7, encoded in the "off3" field. |
The description of MOVA (array to vector, four registers) gives the operational pseudocode for this instruction.
If FEAT_SVE2 is implemented or FEAT_SME is implemented, then if PSTATE.DIT is 1:
Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45
Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.