Move vector register to ZT0
Copy the source vector register to ZT0 at the vector length offset specified by the immediate index. When the index is zero, the instruction writes zeroes to the most significant (512-VL) bits of the ZT0 register. When the index is not zero, the unindexed portions of ZT0 remain unchanged.
This instruction is unpredicated.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | off2 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | Zt | |||||
if !IsFeatureImplemented(FEAT_SME_LUTv2) then UNDEFINED; constant integer t = UInt(Zt); constant integer imm = UInt(off2);
| <offs> |
Is the vector length offset, in the range 0 to 3, defaulting to 0 when omitted, encoded in the "off2" field. |
| <Zt> |
Is the name of the scalable vector register to be transferred, encoded in the "Zt" field. |
CheckStreamingSVEEnabled(); CheckSMEZT0Enabled(); constant integer VL = CurrentVL; constant integer tsize = if VL <= 512 then VL else 512; constant integer offset = imm MOD (512 DIV tsize); bits(512) result = if imm == 0 then Zeros(512) else ZT0[512]; Elem[result, offset, tsize] = Z[t, VL]<tsize-1:0>; ZT0[512] = result;
If PSTATE.DIT is 1:
Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45
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