Performs a rotation right of a value held in a general purpose register by an immediate value, and then inserts a selection of the bottom four bits of the result of the rotation into the PSTATE flags, under the control of a second immediate mask.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | imm6 | 0 | 0 | 0 | 0 | 1 | Rn | 0 | mask | ||||||||||||
| sf | op | S | o2 | ||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_FlagM) then UNDEFINED; constant integer imm = UInt(imm6); bits(4) flagmask = mask; integer n = UInt(Rn);
| <Xn> |
Is the 64-bit name of the general-purpose source register, encoded in the "Rn" field. |
| <shift> |
Is the shift amount, in the range 0 to 63, defaulting to 0 and encoded in the "imm6" field, |
| <mask> |
Is the flag bit mask, an immediate in the range 0 to 15, which selects the bits that are inserted into the NZCV condition flags, encoded in the "mask" field. |
bits(64) reg = X[n, 64]; bits(4) flags = (reg:reg)<imm+3:imm>; if flagmask<3> == '1' then PSTATE.N = flags<3>; if flagmask<2> == '1' then PSTATE.Z = flags<2>; if flagmask<1> == '1' then PSTATE.C = flags<1>; if flagmask<0> == '1' then PSTATE.V = flags<0>;
If PSTATE.DIT is 1:
Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45
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