SCVTF

Signed integer convert to floating-point (predicated)

Convert to floating-point from the signed integer in each active element of the source vector, and place the results in the corresponding elements of the destination vector. Inactive elements in the destination vector register remain unmodified.

If the input and result types have a different size the smaller type is held unpacked in the least significant bits of elements of the larger size. When the input is the smaller type the upper bits of each source element are ignored. When the result is the smaller type the results are zero-extended to fill each destination element.

It has encodings from 7 classes: 16-bit to half-precision , 32-bit to half-precision , 32-bit to single-precision , 32-bit to double-precision , 64-bit to half-precision , 64-bit to single-precision and 64-bit to double-precision

16-bit to half-precision

313029282726252423222120191817161514131211109876543210
0110010101010010101PgZnZd
int_U

SCVTF <Zd>.H, <Pg>/M, <Zn>.H

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 16; constant integer g = UInt(Pg); constant integer n = UInt(Zn); constant integer d = UInt(Zd); constant integer s_esize = 16; constant integer d_esize = 16; constant boolean unsigned = FALSE; constant FPRounding rounding = FPRoundingMode(FPCR);

32-bit to half-precision

313029282726252423222120191817161514131211109876543210
0110010101010100101PgZnZd
int_U

SCVTF <Zd>.H, <Pg>/M, <Zn>.S

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 32; constant integer g = UInt(Pg); constant integer n = UInt(Zn); constant integer d = UInt(Zd); constant integer s_esize = 32; constant integer d_esize = 16; constant boolean unsigned = FALSE; constant FPRounding rounding = FPRoundingMode(FPCR);

32-bit to single-precision

313029282726252423222120191817161514131211109876543210
0110010110010100101PgZnZd
int_U

SCVTF <Zd>.S, <Pg>/M, <Zn>.S

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 32; constant integer g = UInt(Pg); constant integer n = UInt(Zn); constant integer d = UInt(Zd); constant integer s_esize = 32; constant integer d_esize = 32; constant boolean unsigned = FALSE; constant FPRounding rounding = FPRoundingMode(FPCR);

32-bit to double-precision

313029282726252423222120191817161514131211109876543210
0110010111010000101PgZnZd
int_U

SCVTF <Zd>.D, <Pg>/M, <Zn>.S

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 64; constant integer g = UInt(Pg); constant integer n = UInt(Zn); constant integer d = UInt(Zd); constant integer s_esize = 32; constant integer d_esize = 64; constant boolean unsigned = FALSE; constant FPRounding rounding = FPRoundingMode(FPCR);

64-bit to half-precision

313029282726252423222120191817161514131211109876543210
0110010101010110101PgZnZd
int_U

SCVTF <Zd>.H, <Pg>/M, <Zn>.D

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 64; constant integer g = UInt(Pg); constant integer n = UInt(Zn); constant integer d = UInt(Zd); constant integer s_esize = 64; constant integer d_esize = 16; constant boolean unsigned = FALSE; constant FPRounding rounding = FPRoundingMode(FPCR);

64-bit to single-precision

313029282726252423222120191817161514131211109876543210
0110010111010100101PgZnZd
int_U

SCVTF <Zd>.S, <Pg>/M, <Zn>.D

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 64; constant integer g = UInt(Pg); constant integer n = UInt(Zn); constant integer d = UInt(Zd); constant integer s_esize = 64; constant integer d_esize = 32; constant boolean unsigned = FALSE; constant FPRounding rounding = FPRoundingMode(FPCR);

64-bit to double-precision

313029282726252423222120191817161514131211109876543210
0110010111010110101PgZnZd
int_U

SCVTF <Zd>.D, <Pg>/M, <Zn>.D

if !IsFeatureImplemented(FEAT_SVE) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer esize = 64; constant integer g = UInt(Pg); constant integer n = UInt(Zn); constant integer d = UInt(Zd); constant integer s_esize = 64; constant integer d_esize = 64; constant boolean unsigned = FALSE; constant FPRounding rounding = FPRoundingMode(FPCR);

Assembler Symbols

<Zd>

Is the name of the destination scalable vector register, encoded in the "Zd" field.

<Pg>

Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Zn>

Is the name of the source scalable vector register, encoded in the "Zn" field.

Operation

CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; constant bits(PL) mask = P[g, PL]; constant bits(VL) operand = if AnyActiveElement(mask, esize) then Z[n, VL] else Zeros(VL); bits(VL) result = Z[d, VL]; for e = 0 to elements-1 if ActivePredicateElement(mask, e, esize) then constant bits(esize) element = Elem[operand, e, esize]; constant bits(d_esize) fpval = FixedToFP(element<s_esize-1:0>, 0, unsigned, FPCR, rounding, d_esize); Elem[result, e, esize] = ZeroExtend(fpval, esize); Z[d, VL] = result;

Operational information

This instruction might be immediately preceded in program order by a MOVPRFX instruction. The MOVPRFX must conform to all of the following requirements, otherwise the behavior of the MOVPRFX and this instruction is constrained unpredictable:


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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