SHA512SU0

SHA512 Schedule Update 0 takes the values from the two 128-bit source SIMD&FP registers and produces a 128-bit output value that combines the gamma0 functions of two iterations of the SHA512 schedule update that are performed after the first 16 iterations within a block. It returns this value to the destination SIMD&FP register.

Advanced SIMD
(FEAT_SHA512)

313029282726252423222120191817161514131211109876543210
1100111011000000100000RnRd
opcode

SHA512SU0 <Vd>.2D, <Vn>.2D

if !IsFeatureImplemented(FEAT_SHA512) then UNDEFINED; integer d = UInt(Rd); integer n = UInt(Rn);

Assembler Symbols

<Vd>

Is the name of the SIMD&FP source and destination register, encoded in the "Rd" field.

<Vn>

Is the name of the second SIMD&FP source register, encoded in the "Rn" field.

Operation

AArch64.CheckFPAdvSIMDEnabled(); bits(64) sig0; bits(128) Vtmp; bits(128) x = V[n, 128]; bits(128) w = V[d, 128]; sig0 = ROR(w<127:64>, 1) EOR ROR(w<127:64>, 8) EOR ('0000000':w<127:71>); Vtmp<63:0> = w<63:0> + sig0; sig0 = ROR(x<63:0>, 1) EOR ROR(x<63:0>, 8) EOR ('0000000':x<63:7>); Vtmp<127:64> = w<127:64> + sig0; V[d, 128] = Vtmp;

Operational information

If PSTATE.DIT is 1:


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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