SMINV

Signed Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are signed integer values.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

313029282726252423222120191817161514131211109876543210
0Q001110size110001101010RnRd
Uop

SMINV <V><d>, <Vn>.<T>

integer d = UInt(Rd); integer n = UInt(Rn); if size:Q == '100' then UNDEFINED; if size == '11' then UNDEFINED; constant integer esize = 8 << UInt(size); constant integer datasize = 64 << UInt(Q); integer elements = datasize DIV esize; boolean unsigned = (U == '1'); boolean min = (op == '1');

Assembler Symbols

<V>

Is the destination width specifier, encoded in size:

size <V>
00 B
01 H
10 S
11 RESERVED
<d>

Is the number of the SIMD&FP destination register, encoded in the "Rd" field.

<Vn>

Is the name of the SIMD&FP source register, encoded in the "Rn" field.

<T>

Is an arrangement specifier, encoded in size:Q:

size Q <T>
00 0 8B
00 1 16B
01 0 4H
01 1 8H
10 0 RESERVED
10 1 4S
11 x RESERVED

Operation

CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n, datasize]; integer maxmin; integer element; maxmin = Int(Elem[operand, 0, esize], unsigned); for e = 1 to elements-1 element = Int(Elem[operand, e, esize], unsigned); maxmin = if min then Min(maxmin, element) else Max(maxmin, element); V[d, esize] = maxmin<esize-1:0>;

Operational information

If PSTATE.DIT is 1:


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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