SQRSHRUNT

Signed saturating rounding shift right unsigned narrow by immediate (top)

Shift each signed integer value in the source vector elements right by an immediate value, and place the rounded results in the odd-numbered half-width destination elements, leaving the even-numbered elements unchanged. Each result element is saturated to the half-width N-bit element's unsigned integer range 0 to (2N)-1. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. This instruction is unpredicated.

313029282726252423222120191817161514131211109876543210
010001010tszh1tszlimm3000011ZnZd
URT

SQRSHRUNT <Zd>.<T>, <Zn>.<Tb>, #<const>

if !IsFeatureImplemented(FEAT_SVE2) && !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant bits(3) tsize = tszh:tszl; if tsize == '000' then UNDEFINED; constant integer esize = 8 << HighestSetBit(tsize); constant integer n = UInt(Zn); constant integer d = UInt(Zd); constant integer shift = (2 * esize) - UInt(tsize:imm3);

Assembler Symbols

<Zd>

Is the name of the destination scalable vector register, encoded in the "Zd" field.

<T>

Is the size specifier, encoded in tszh:tszl:

tszh tszl <T>
0 00 RESERVED
0 01 B
0 1x H
1 xx S
<Zn>

Is the name of the source scalable vector register, encoded in the "Zn" field.

<Tb>

Is the size specifier, encoded in tszh:tszl:

tszh tszl <Tb>
0 00 RESERVED
0 01 H
0 1x S
1 xx D
<const>

Is the immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3".

Operation

CheckSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV (2 * esize); constant bits(VL) operand = Z[n, VL]; bits(VL) result = Z[d, VL]; for e = 0 to elements-1 constant bits(2*esize) element = Elem[operand, e, 2*esize]; constant integer res = (SInt(element) + (1 << (shift-1))) >> shift; Elem[result, 2*e + 1, esize] = UnsignedSat(res, esize); Z[d, VL] = result;


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.