SRI

Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.

The following figure shows an example of the operation of shift right by 3 for an 8-bit vector element.
shift right by 3 for an 8-bit vector element

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

It has encodings from 2 classes: Scalar and Vector

Scalar

313029282726252423222120191817161514131211109876543210
0111111101xxximmb010001RnRd
Uimmhopcode

SRI D<d>, D<n>, #<shift>

integer d = UInt(Rd); integer n = UInt(Rn); if immh<3> != '1' then UNDEFINED; constant integer esize = 8 << 3; constant integer datasize = esize; integer elements = 1; integer shift = (esize * 2) - UInt(immh:immb);

Vector

313029282726252423222120191817161514131211109876543210
0Q1011110!= 0000immb010001RnRd
Uimmhopcode

SRI <Vd>.<T>, <Vn>.<T>, #<shift>

integer d = UInt(Rd); integer n = UInt(Rn); if immh == '0000' then SEE(asimdimm); if immh<3>:Q == '10' then UNDEFINED; constant integer esize = 8 << HighestSetBit(immh); constant integer datasize = 64 << UInt(Q); integer elements = datasize DIV esize; integer shift = (esize * 2) - UInt(immh:immb);

Assembler Symbols

<d>

Is the number of the SIMD&FP destination register, in the "Rd" field.

<n>

Is the number of the first SIMD&FP source register, encoded in the "Rn" field.

<shift>

For the scalar variant: is the right shift amount, in the range 1 to 64, encoded as 128 - UInt("immh:immb").

For the vector variant: is the right shift amount, in the range 1 to the element width in bits, encoded in immh:immb:

immh <shift>
0001 16 - UInt(immh:immb)
001x 32 - UInt(immh:immb)
01xx 64 - UInt(immh:immb)
1xxx 128 - UInt(immh:immb)
<Vd>

Is the name of the SIMD&FP destination register, encoded in the "Rd" field.

<T>

Is an arrangement specifier, encoded in immh:Q:

immh Q <T>
0001 0 8B
0001 1 16B
001x 0 4H
001x 1 8H
01xx 0 2S
01xx 1 4S
1xxx 0 RESERVED
1xxx 1 2D
<Vn>

Is the name of the SIMD&FP source register, encoded in the "Rn" field.

Operation

CheckFPAdvSIMDEnabled64(); bits(datasize) operand = V[n, datasize]; bits(datasize) operand2 = V[d, datasize]; bits(datasize) result; bits(esize) mask = LSR(Ones(esize), shift); bits(esize) shifted; for e = 0 to elements-1 shifted = LSR(Elem[operand, e, esize], shift); Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted; V[d, datasize] = result;

Operational information

If PSTATE.DIT is 1:


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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