SRSRA

Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSRA.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

It has encodings from 2 classes: Scalar and Vector

Scalar

integer d = UInt(Rd); integer n = UInt(Rn); if immh<3> != '1' then UNDEFINED; constant integer esize = 8 << 3; constant integer datasize = esize; integer elements = 1; integer shift = (esize * 2) - UInt(immh:immb); boolean unsigned = (U == '1'); boolean round = (o1 == '1'); boolean accumulate = (o0 == '1');

Vector

integer d = UInt(Rd); integer n = UInt(Rn); if immh == '0000' then SEE(asimdimm); if immh<3>:Q == '10' then UNDEFINED; constant integer esize = 8 << HighestSetBit(immh); constant integer datasize = 64 << UInt(Q); integer elements = datasize DIV esize; integer shift = (esize * 2) - UInt(immh:immb); boolean unsigned = (U == '1'); boolean round = (o1 == '1'); boolean accumulate = (o0 == '1');