Scatter store doublewords from a vector (immediate index)
Scatter store of doublewords from the active elements of a vector register to the memory addresses generated by a vector base plus immediate index. The index is a multiple of 8 in the range 0 to 248. Inactive elements are not written to memory.
This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | imm5 | 1 | 0 | 1 | Pg | Zn | Zt | ||||||||||||||
| msz<1> | msz<0> | ||||||||||||||||||||||||||||||
if !IsFeatureImplemented(FEAT_SVE) then UNDEFINED; constant integer t = UInt(Zt); constant integer n = UInt(Zn); constant integer g = UInt(Pg); constant integer esize = 64; constant integer msize = 64; constant integer offset = UInt(imm5);
| <Zt> |
Is the name of the scalable vector register to be transferred, encoded in the "Zt" field. |
| <Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
| <Zn> |
Is the name of the base scalable vector register, encoded in the "Zn" field. |
| <imm> |
Is the optional unsigned immediate byte offset, a multiple of 8 in the range 0 to 248, defaulting to 0, encoded in the "imm5" field. |
CheckNonStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; constant bits(PL) mask = P[g, PL]; bits(VL) base; bits(VL) src; constant integer mbytes = msize DIV 8; constant boolean contiguous = FALSE; constant boolean nontemporal = FALSE; constant boolean tagchecked = TRUE; constant AccessDescriptor accdesc = CreateAccDescSVE(MemOp_STORE, nontemporal, contiguous, tagchecked); if AnyActiveElement(mask, esize) then base = Z[n, VL]; src = Z[t, VL]; for e = 0 to elements-1 if ActivePredicateElement(mask, e, esize) then constant bits(64) baddr = ZeroExtend(Elem[base, e, esize], 64); constant bits(64) addr = AddressAdd(baddr, offset * mbytes, accdesc); Mem[addr, mbytes, accdesc] = Elem[src, e, esize]<msize-1:0>;
If FEAT_SVE2 is implemented or FEAT_SME is implemented, then if PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored when its governing predicate register contains the same value for each execution.
Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45
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