ST1H (scalar plus vector)

Scatter store of halfwords from the active elements of a vector register to the memory addresses generated by a 64-bit scalar base plus vector index. The index values are optionally first sign or zero-extended from 32 to 64 bits and then optionally multiplied by 2. Inactive elements are not written to memory.

This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.

32-bit scaled offset

if !IsFeatureImplemented(FEAT_SVE) then UNDEFINED; constant integer t = UInt(Zt); constant integer n = UInt(Rn); constant integer m = UInt(Zm); constant integer g = UInt(Pg); constant integer esize = 32; constant integer msize = 16; constant integer offs_size = 32; constant boolean offs_unsigned = xs == '0'; constant integer scale = 1;

32-bit unpacked scaled offset

if !IsFeatureImplemented(FEAT_SVE) then UNDEFINED; constant integer t = UInt(Zt); constant integer n = UInt(Rn); constant integer m = UInt(Zm); constant integer g = UInt(Pg); constant integer esize = 64; constant integer msize = 16; constant integer offs_size = 32; constant boolean offs_unsigned = xs == '0'; constant integer scale = 1;

32-bit unpacked unscaled offset

if !IsFeatureImplemented(FEAT_SVE) then UNDEFINED; constant integer t = UInt(Zt); constant integer n = UInt(Rn); constant integer m = UInt(Zm); constant integer g = UInt(Pg); constant integer esize = 64; constant integer msize = 16; constant integer offs_size = 32; constant boolean offs_unsigned = xs == '0'; constant integer scale = 0;

32-bit unscaled offset

64-bit scaled offset

if !IsFeatureImplemented(FEAT_SVE) then UNDEFINED; constant integer t = UInt(Zt); constant integer n = UInt(Rn); constant integer m = UInt(Zm); constant integer g = UInt(Pg); constant integer esize = 64; constant integer msize = 16; constant integer offs_size = 64; constant boolean offs_unsigned = TRUE; constant integer scale = 1;

64-bit unscaled offset

if !IsFeatureImplemented(FEAT_SVE) then UNDEFINED; constant integer t = UInt(Zt); constant integer n = UInt(Rn); constant integer m = UInt(Zm); constant integer g = UInt(Pg); constant integer esize = 64; constant integer msize = 16; constant integer offs_size = 64; constant boolean offs_unsigned = TRUE; constant integer scale = 0;

Assembler Symbols

<Zt>	Is the name of the scalable vector register to be transferred, encoded in the "Zt" field.

<Pg>	Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<Zm>	Is the name of the offset scalable vector register, encoded in the "Zm" field.

<mod>

Is the index extend and shift specifier, encoded in xs:

xs	<mod>
0	UXTW
1	SXTW

Operation

CheckNonStreamingSVEEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer elements = VL DIV esize; bits(64) base; constant bits(PL) mask = P[g, PL]; bits(VL) offset; bits(VL) src; constant integer mbytes = msize DIV 8; constant boolean contiguous = FALSE; constant boolean nontemporal = FALSE; constant boolean tagchecked = TRUE; constant AccessDescriptor accdesc = CreateAccDescSVE(MemOp_STORE, nontemporal, contiguous, tagchecked); if !AnyActiveElement(mask, esize) then if n == 31 && ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE) then CheckSPAlignment(); else if n == 31 then CheckSPAlignment(); base = if n == 31 then SP[] else X[n, 64]; offset = Z[m, VL]; src = Z[t, VL]; for e = 0 to elements-1 if ActivePredicateElement(mask, e, esize) then constant integer off = Int(Elem[offset, e, esize]<offs_size-1:0>, offs_unsigned); constant bits(64) addr = AddressAdd(base, off << scale, accdesc); Mem[addr, mbytes, accdesc] = Elem[src, e, esize]<msize-1:0>;

Operational information

If FEAT_SVE2 is implemented or FEAT_SME is implemented, then if PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored when its governing predicate register contains the same value for each execution.

Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	0	0	1	0	0	1	1	1	Zm					1	xs	0	Pg			Rn					Zt
							msz<1>	msz<0>

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	0	0	1	0	0	1	0	1	Zm					1	xs	0	Pg			Rn					Zt
							msz<1>	msz<0>

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	0	0	1	0	0	1	0	0	Zm					1	xs	0	Pg			Rn					Zt
							msz<1>	msz<0>

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	0	0	1	0	0	1	1	0	Zm					1	xs	0	Pg			Rn					Zt
							msz<1>	msz<0>

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	0	0	1	0	0	1	0	1	Zm					1	0	1	Pg			Rn					Zt
							msz<1>	msz<0>