Contiguous store of quadwords from 128-bit element ZA tile slice
The slice number in the tile is selected by the slice index register, modulo the number of 128-bit elements in a Streaming SVE vector. The memory address is generated by scalar base and optional scalar offset which is multiplied by 16 and added to the base address. Inactive elements are not written to memory.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | Rm | V | Rs | Pg | Rn | 0 | ZAt | ||||||||||||||
if !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer n = UInt(Rn); constant integer m = UInt(Rm); constant integer g = UInt('0':Pg); constant integer s = UInt('011':Rs); constant integer t = UInt(ZAt); constant integer offset = 0; constant integer esize = 128; constant boolean vertical = V == '1';
| <ZAt> |
Is the name of the ZA tile ZA0-ZA15 to be accessed, encoded in the "ZAt" field. |
| <HV> |
Is the horizontal or vertical slice indicator,
encoded in
|
| <Ws> |
Is the 32-bit name of the slice index register W12-W15, encoded in the "Rs" field. |
| <offs> |
Is the slice index offset, with implicit value 0. |
| <Pg> |
Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
| <Xm> |
Is the optional 64-bit name of the general-purpose offset register, defaulting to XZR, encoded in the "Rm" field. |
CheckStreamingSVEAndZAEnabled(); constant integer VL = CurrentVL; constant integer PL = VL DIV 8; constant integer dim = VL DIV esize; bits(64) base; bits(64) addr; constant bits(PL) mask = P[g, PL]; bits(64) moffs = X[m, 64]; constant bits(32) index = X[s, 32]; constant integer slice = (UInt(index) + offset) MOD dim; bits(VL) src; constant integer mbytes = esize DIV 8; constant boolean contiguous = TRUE; constant boolean nontemporal = FALSE; constant boolean tagchecked = TRUE; constant AccessDescriptor accdesc = CreateAccDescSME(MemOp_STORE, nontemporal, contiguous, tagchecked); if n == 31 then if (AnyActiveElement(mask, esize) || ConstrainUnpredictableBool(Unpredictable_CHECKSPNONEACTIVE)) then CheckSPAlignment(); base = SP[]; else base = X[n, 64]; src = ZAslice[t, esize, vertical, slice, VL]; for e = 0 to dim-1 addr = AddressAdd(base, UInt(moffs) * mbytes, accdesc); if ActivePredicateElement(mask, e, esize) then Mem[addr, mbytes, accdesc] = Elem[src, e, esize]; moffs = moffs + 1;
If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored when its governing predicate register contains the same value for each execution.
Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45
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