Store-Release SIMD&FP Register (unscaled offset). This instruction stores a single SIMD&FP register to memory. The address that is used for the store is calculated from a base register value and an optional immediate offset.
The instruction has memory ordering semantics, as described in Load-Acquire, Load-AcquirePC, and Store-Release.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| size | 0 | 1 | 1 | 1 | 0 | 1 | x | 0 | 0 | imm9 | 1 | 0 | Rn | Rt | |||||||||||||||||
| opc | |||||||||||||||||||||||||||||||
integer scale = UInt(opc<1>:size); if scale > 4 then UNDEFINED; bits(64) offset = SignExtend(imm9, 64);
| <Bt> |
Is the 8-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
| <simm> |
Is the optional signed immediate byte offset, in the range -256 to 255, defaulting to 0 and encoded in the "imm9" field. |
| <Ht> |
Is the 16-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field. |
| <St> |
Is the 32-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field. |
| <Dt> |
Is the 64-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field. |
| <Qt> |
Is the 128-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field. |
integer t = UInt(Rt); integer n = UInt(Rn); constant integer datasize = 8 << scale; boolean nontemporal = FALSE; boolean tagchecked = n != 31;
CheckFPAdvSIMDEnabled64(); bits(64) address; AccessDescriptor accdesc = CreateAccDescASIMDAcqRel(MemOp_STORE, tagchecked); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; address = AddressAdd(address, offset, accdesc); Mem[address, datasize DIV 8, accdesc] = V[t, datasize];
If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.
Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45
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