Store-Release Exclusive Register stores a 32-bit word or a 64-bit doubleword to memory if the PE has exclusive access to the memory address, from two registers, and returns a status value of 0 if the store was successful, or of 1 if no store was performed. See Synchronization and semaphores. The memory access is atomic. The instruction also has memory ordering semantics as described in Load-Acquire, Store-Release. For information about addressing modes, see Load/Store addressing modes.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | x | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | Rs | 1 | (1) | (1) | (1) | (1) | (1) | Rn | Rt | ||||||||||||
| size | L | o0 | Rt2 | ||||||||||||||||||||||||||||
integer s = UInt(Rs); integer t = UInt(Rt); integer n = UInt(Rn); constant integer elsize = 8 << UInt(size); boolean tagchecked = n != 31; boolean rt_unknown = FALSE; boolean rn_unknown = FALSE; if s == t then Constraint c = ConstrainUnpredictable(Unpredictable_DATAOVERLAP); assert c IN {Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_UNKNOWN rt_unknown = TRUE; // store UNKNOWN value when Constraint_UNDEF UNDEFINED; when Constraint_NOP EndOfInstruction(); if s == n && n != 31 then Constraint c = ConstrainUnpredictable(Unpredictable_BASEOVERLAP); assert c IN {Constraint_UNKNOWN, Constraint_UNDEF, Constraint_NOP}; case c of when Constraint_UNKNOWN rn_unknown = TRUE; // address is UNKNOWN when Constraint_UNDEF UNDEFINED; when Constraint_NOP EndOfInstruction();
For information about the CONSTRAINED UNPREDICTABLE behavior of this instruction, see Architectural Constraints on UNPREDICTABLE behaviors, and particularly STLXR.
| <Wt> |
Is the 32-bit name of the general-purpose register to be transferred, encoded in the "Rt" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
| <Xt> |
Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field. |
Aborts and alignment
If a synchronous Data Abort exception is generated by the execution of this instruction:
Accessing an address that is not aligned to the size of the data being accessed causes an Alignment fault Data Abort exception to be generated, subject to the following rules:
If AArch64.ExclusiveMonitorsPass() returns FALSE and the memory address, if accessed, would generate a synchronous Data Abort exception, it is IMPLEMENTATION DEFINED whether the exception is generated.
bits(64) address; bits(elsize) data; constant integer dbytes = elsize DIV 8; AccessDescriptor accdesc = CreateAccDescExLDST(MemOp_STORE, TRUE, tagchecked); if n == 31 then CheckSPAlignment(); address = SP[]; elsif rn_unknown then address = bits(64) UNKNOWN; else address = X[n, 64]; if rt_unknown then data = bits(elsize) UNKNOWN; else data = X[t, elsize]; bit status = '1'; // Check whether the Exclusives monitors are set to include the // physical memory locations corresponding to virtual address // range [address, address+dbytes-1]. // If AArch64.ExclusiveMonitorsPass() returns FALSE and the memory address, // if accessed, would generate a synchronous Data Abort exception, it is // IMPLEMENTATION DEFINED whether the exception is generated. // It is a limitation of this model that synchronous Data Aborts are never // generated in this case, as Mem[] is not called. // If FEAT_SPE is implemented, it is also IMPLEMENTATION DEFINED whether or not the // physical address packet is output when permitted and when // AArch64.ExclusiveMonitorPass() returns FALSE for a Store Exclusive instruction. // This behavior is not reflected here due to the previously stated limitation. if AArch64.ExclusiveMonitorsPass(address, dbytes, accdesc) then // This atomic write will be rejected if it does not refer // to the same physical locations after address translation. Mem[address, dbytes, accdesc] = data; status = ExclusiveMonitorsStatus(); X[s, 32] = ZeroExtend(status, 32);
If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.
Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45
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