STR (immediate, SIMD&FP) -- A64

Store SIMD&FP register (immediate offset). This instruction stores a single SIMD&FP register to memory. The address that is used for the store is calculated from a base register value and an immediate offset.

Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Post-index

integer scale = UInt(opc<1>:size); if scale > 4 then UNDEFINED; boolean wback = TRUE; boolean postindex = TRUE; bits(64) offset = SignExtend(imm9, 64);

Pre-index

integer scale = UInt(opc<1>:size); if scale > 4 then UNDEFINED; boolean wback = TRUE; boolean postindex = FALSE; bits(64) offset = SignExtend(imm9, 64);

Unsigned offset

integer scale = UInt(opc<1>:size); if scale > 4 then UNDEFINED; boolean wback = FALSE; boolean postindex = FALSE; bits(64) offset = LSL(ZeroExtend(imm12, 64), scale);

Assembler Symbols

<Bt>	Is the 8-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

<simm>

Is the signed immediate byte offset, in the range -256 to 255, encoded in the "imm9" field.

<Ht>	Is the 16-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.

<St>	Is the 32-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.

<Dt>	Is the 64-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.

<Qt>	Is the 128-bit name of the SIMD&FP register to be transferred, encoded in the "Rt" field.

<pimm>	For the 8-bit variant: is the optional positive immediate byte offset, in the range 0 to 4095, defaulting to 0 and encoded in the "imm12" field.
	For the 16-bit variant: is the optional positive immediate byte offset, a multiple of 2 in the range 0 to 8190, defaulting to 0 and encoded in the "imm12" field as <pimm>/2.
	For the 32-bit variant: is the optional positive immediate byte offset, a multiple of 4 in the range 0 to 16380, defaulting to 0 and encoded in the "imm12" field as <pimm>/4.
	For the 64-bit variant: is the optional positive immediate byte offset, a multiple of 8 in the range 0 to 32760, defaulting to 0 and encoded in the "imm12" field as <pimm>/8.
	For the 128-bit variant: is the optional positive immediate byte offset, a multiple of 16 in the range 0 to 65520, defaulting to 0 and encoded in the "imm12" field as <pimm>/16.

Shared Decode

integer t = UInt(Rt); integer n = UInt(Rn); constant integer datasize = 8 << scale; boolean nontemporal = FALSE; boolean tagchecked = wback || n != 31;

Operation

CheckFPEnabled64(); bits(64) address; AccessDescriptor accdesc = CreateAccDescASIMD(MemOp_STORE, nontemporal, tagchecked); if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; if !postindex then address = AddressAdd(address, offset, accdesc); Mem[address, datasize DIV 8, accdesc] = V[t, datasize]; if wback then if postindex then address = AddressAdd(address, offset, accdesc); if n == 31 then SP[] = address; else X[n, 64] = address;

Operational information

If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.

Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45