Store ZA array vector
The ZA array vector is selected by the sum of the vector select register and immediate offset, modulo the number of bytes in a Streaming SVE vector. The immediate offset is in the range 0 to 15. The memory address is generated by a 64-bit scalar base, plus the same optional immediate offset multiplied by the current vector length in bytes. This instruction is unpredicated.
The store is performed as contiguous byte accesses, with no endian conversion and no guarantee of single-copy atomicity larger than a byte. However, if alignment is checked, then the base register must be aligned to 16 bytes.
This instruction does not require the PE to be in Streaming SVE mode, and it is expected that this instruction will not experience a significant slowdown due to contention with other PEs that are executing in Streaming SVE mode.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | Rv | 0 | 0 | 0 | Rn | 0 | off4 | ||||||||
if !IsFeatureImplemented(FEAT_SME) then UNDEFINED; constant integer n = UInt(Rn); constant integer v = UInt('011':Rv); constant integer offset = UInt(off4);
| <Wv> |
Is the 32-bit name of the vector select register W12-W15, encoded in the "Rv" field. |
| <offs> |
Is the vector select offset and optional memory offset, in the range 0 to 15, defaulting to 0, encoded in the "off4" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
CheckSMEAndZAEnabled(); constant integer SVL = CurrentSVL; constant integer dim = SVL DIV 8; bits(64) base; constant integer moffs = offset * dim; bits(SVL) src; constant bits(32) vbase = X[v, 32]; constant integer vec = (UInt(vbase) + offset) MOD dim; constant boolean contiguous = TRUE; constant boolean nontemporal = FALSE; constant boolean tagchecked = n != 31; constant AccessDescriptor accdesc = CreateAccDescSME(MemOp_STORE, nontemporal, contiguous, tagchecked); if IsFeatureImplemented(FEAT_TME) && TSTATE.depth > 0 then FailTransaction(TMFailure_ERR, FALSE); if n == 31 then CheckSPAlignment(); base = SP[]; else base = X[n, 64]; src = ZAvector[vec, SVL]; bits(64) addr = AddressAdd(base, moffs, accdesc); constant boolean aligned = IsAligned(addr, 16); if !aligned && AlignmentEnforced() then AArch64.Abort(addr, AlignmentFault(accdesc)); for e = 0 to dim-1 AArch64.MemSingle[addr, 1, accdesc, aligned] = Elem[src, e, 8]; addr = AddressIncrement(addr, 1, accdesc);
If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.
Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45
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