STR (table)

Store ZT0 register

Store the 64-byte ZT0 register to the memory address provided in the 64-bit scalar base register. This instruction is unpredicated.

The store is performed as contiguous byte accesses, with no endian conversion and no guarantee of single-copy atomicity larger than a byte. However, if alignment is checked, then the base register must be aligned to 16 bytes.

This instruction does not require the PE to be in Streaming SVE mode, and it is expected that this instruction will not experience a significant slowdown due to contention with other PEs that are executing in Streaming SVE mode.

SME2
(FEAT_SME2)

313029282726252423222120191817161514131211109876543210
1110000100111111100000Rn00000

STR ZT0, [<Xn|SP>]

if !IsFeatureImplemented(FEAT_SME2) then UNDEFINED; constant integer n = UInt(Rn);

Assembler Symbols

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field.

Operation

CheckSMEEnabled(); CheckSMEZT0Enabled(); constant integer elements = 512 DIV 8; bits(64) addr; constant bits(512) table = ZT0[512]; constant boolean contiguous = TRUE; constant boolean nontemporal = FALSE; constant boolean tagchecked = n != 31; constant AccessDescriptor accdesc = CreateAccDescSME(MemOp_STORE, nontemporal, contiguous, tagchecked); if IsFeatureImplemented(FEAT_TME) && TSTATE.depth > 0 then FailTransaction(TMFailure_ERR, FALSE); if n == 31 then CheckSPAlignment(); addr = SP[]; else addr = X[n, 64]; constant boolean aligned = IsAligned(addr, 16); if !aligned && AlignmentEnforced() then AArch64.Abort(addr, AlignmentFault(accdesc)); for e = 0 to elements-1 AArch64.MemSingle[addr, 1, accdesc, aligned] = Elem[table, e, 8]; addr = AddressIncrement(addr, 1, accdesc);

Operational information

If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

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