Atomic unsigned minimum on word or doubleword in memory, without return, atomically loads a 32-bit word or 64-bit doubleword from memory, compares it against the value held in a register, and stores the smaller value back to memory, treating the values as unsigned numbers.
For information about addressing modes, see Load/Store addressing modes.
This is an alias of LDUMIN, LDUMINA, LDUMINAL, LDUMINL. This means:
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| 1 | x | 1 | 1 | 1 | 0 | 0 | 0 | 0 | R | 1 | Rs | 0 | 1 | 1 | 1 | 0 | 0 | Rn | 1 | 1 | 1 | 1 | 1 | ||||||||
| size | VR | A | o3 | opc | Rt | ||||||||||||||||||||||||||
is equivalent to
and is always the preferred disassembly.
is equivalent to
and is always the preferred disassembly.
| <Ws> |
Is the 32-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field. |
| <Xn|SP> |
Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Rn" field. |
| <Xs> |
Is the 64-bit name of the general-purpose register holding the data value to be operated on with the contents of the memory location, encoded in the "Rs" field. |
The description of LDUMIN, LDUMINA, LDUMINAL, LDUMINL gives the operational pseudocode for this instruction.
If PSTATE.DIT is 1, the timing of this instruction is insensitive to the value of the data being loaded or stored.
Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45
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