STZGM

Store Tag and Zero Multiple writes a naturally aligned block of N Allocation Tags and stores zero to the associated data locations, where the size of N is identified in DCZID_EL0.BS, and the Allocation Tag is taken from the source register bits<3:0>.

This instruction is UNDEFINED at EL0.

This instruction generates an Unchecked access.

Integer
(FEAT_MTE2)

313029282726252423222120191817161514131211109876543210
1101100100100000000000XnXt
opcimm9op2

STZGM <Xt>, [<Xn|SP>]

if !IsFeatureImplemented(FEAT_MTE2) then UNDEFINED; integer t = UInt(Xt); integer n = UInt(Xn);

Assembler Symbols

<Xt>

Is the 64-bit name of the general-purpose source register, encoded in the "Xt" field.

<Xn|SP>

Is the 64-bit name of the general-purpose base register or stack pointer, encoded in the "Xn" field.

Operation

if PSTATE.EL == EL0 then UNDEFINED; bits(64) data = X[t, 64]; bits(4) tag = data<3:0>; bits(64) address; if n == 31 then CheckSPAlignment(); address = SP[]; else address = X[n, 64]; integer size = 4 * (2 ^ (UInt(DCZID_EL0.BS))); address = Align(address, size); integer count = size >> LOG2_TAG_GRANULE; boolean devstoreunpred = TRUE; AccessDescriptor accdesc = CreateAccDescLDGSTG(MemOp_STORE, devstoreunpred); for i = 0 to count-1 AArch64.MemTag[address, accdesc] = tag; Mem[address, TAG_GRANULE, accdesc] = Zeros(8*TAG_GRANULE); address = AddressIncrement(address, TAG_GRANULE, accdesc);


Internal version only: aarchmrs v2024-03_relA, pseudocode v2024-03_rel, sve v2024-03_rel ; Build timestamp: 2024-03-26T09:45

Copyright © 2010-2024 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.